公开(公告)号：US12272640B2

公开(公告)日：2025-04-08

申请号：US18304261

申请日：2023-04-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Zeng Kang ,  Wen-Shen Chou ,  Yung-Chow Peng

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/535 ,  H01L27/06 ,  H01L49/02

Abstract: A semiconductor device includes a plurality of transistors, a plurality of metal layers, and a resistor. The plurality of transistors are connected in series between a power terminal and a ground terminal, and gate terminals of the transistors being connected together. The plurality of metal layers are overlaid above the plurality of transistors. The resistor is implemented between two of the plurality of metal layers.

公开(公告)号：US12272605B2

公开(公告)日：2025-04-08

申请号：US18336168

申请日：2023-06-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsiung Lin ,  Yi-Hsun Chiu ,  Shang-Wen Chang

IPC: H01L21/8238 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522 ,  H01L27/092 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor structure includes a first semiconductor fin and a second semiconductor fin adjacent to the first semiconductor fin. The first and the second semiconductor fins extend lengthwise along a first direction over a substrate. A metal gate structure is disposed over the first and second semiconductor fins, the metal gate structure extending lengthwise along a second direction perpendicular to the first direction. A first epitaxial source/drain (S/D) feature is disposed over the first semiconductor fin, and a second epitaxial S/D feature is disposed over the second semiconductor fin. An interlayer dielectric (ILD) layer is disposed over the first and the second epitaxial S/D features. And an S/D contact is disposed directly above the first and second epitaxial S/D features. The S/D contact directly contacts the first epitaxial S/D feature, and the S/D contact is isolated from the second epitaxial S/D feature by the ILD layer.

公开(公告)号：US20250113596A1

公开(公告)日：2025-04-03

申请号：US18375593

申请日：2023-10-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Chien Huang ,  Cheng-Yin Wang ,  Wei-Cheng Lin ,  Kao-Cheng Lin ,  Szuya Liao

IPC: H01L27/088 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66

Abstract: Embodiments include mixed complementary field effect and unipolar transistors and methods of forming the same. In an embodiment, a structure includes: a first semiconductor nanostructure; a second semiconductor nanostructure; a first isolation structure interposed between the first semiconductor nanostructure and the second semiconductor nanostructure; a first source/drain region extending laterally from an end of the first semiconductor nanostructure, the first source/drain region having a first conductivity type; a second source/drain region extending laterally from an end of the second semiconductor nanostructure, the second source/drain region having the first conductivity type, the second source/drain region aligned vertically with the first source/drain region; and a first gate structure surrounding the first semiconductor nanostructure and the second semiconductor nanostructure.

公开(公告)号：US20250112794A1

公开(公告)日：2025-04-03

申请号：US18981187

申请日：2024-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Lien Linus LU ,  Cheng-En LEE

IPC: H04L9/32 ,  G06F21/75 ,  G11C11/419 ,  H03K3/03

Abstract: Disclosed is a physical unclonable function generator circuit and method. In one embodiment, physical unclonable function (PUF) generator includes: a PUF cell array that comprises a plurality of bit cells, wherein each of the plurality of bit cells comprises at least two access transistors, at least one enable transistor, and at least two storage nodes, wherein the at least two storage nodes are pre-configured with substantially the same voltages allowing each of the plurality of bit cells having a first metastable logical state; a PUF control circuit coupled to the PUF cell array, wherein the PUF control circuit is configured to access the plurality of bit cells to determine second logical states by turning on the at least one enable transistor and turning off the at least two access transistors of each of the plurality of bit cells, and based on the second logical states of the plurality of bit cells, to generate a PUF output; and a noise injector coupled to the PUF control circuit and the PUF cell array, wherein the noise injector is configured to create stressed operation conditions to evaluate stability of the plurality of bit cells.

公开(公告)号：US20250109870A1

公开(公告)日：2025-04-03

申请号：US18979108

申请日：2024-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Wei WU ,  Hao YANG ,  Hsiao-Chieh CHOU ,  Chun-Hung CHAO ,  Jao Sheng HUANG ,  Neng-Jye YANG ,  Kuo-Bin HUANG

IPC: F24F9/00 ,  H01L21/67 ,  H01L21/687

Abstract: The present disclosure is at least directed to utilizing air curtain devices to form air curtains to separate and isolate areas in which respective workpieces are stored from a transfer compartment within a workpiece processing apparatus. The transfer compartment of the workpiece processing apparatus includes a robot configured to transfer or transport ones of the workpieces to and from these respective storage areas through the transfer compartment and to and from a tool compartment. A tool is present in the tool compartment for processing and refining the respective workpieces. Clean dry air (CDA) may be circulated through the respective storage areas. The air curtains formed by the air curtain devices and the circulation of CDA through the respective storage areas reduces the likelihood of the generation of defects, damages, and degradation of the workpieces when present within the workpiece processing apparatus.

公开(公告)号：US12266688B2

公开(公告)日：2025-04-01

申请号：US18331917

申请日：2023-06-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Sung-Li Wang ,  Mrunal A. Khaderbad ,  Yasutoshi Okuno

IPC: H01L29/08 ,  H01L21/02 ,  H01L21/285 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/535 ,  H01L27/092 ,  H01L29/165 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L21/311

Abstract: A semiconductor device includes first and second semiconductor fins extending from a substrate, and first and second epitaxial layers wrapping around the first and second semiconductor fins, respectively. The semiconductor device further includes a contact plug over the first epitaxial layer and the second epitaxial layer. The contact plug includes a first interfacial layer over the first epitaxial layer and a second interfacial layer over the second epitaxial layer. The first and second interfacial layers include a noble metal element and a Group IV element.

公开(公告)号：US12266592B2

公开(公告)日：2025-04-01

申请号：US18324643

申请日：2023-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuan-Yang Hsiao ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/482 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor structure includes a semiconductor substrate and an interconnect structure on the semiconductor structure. The interconnect structure includes a first layer, a second layer over the first layer, a third layer over the second layer, and a fourth layer over the third layer. A first through via extends through the semiconductor substrate, the first layer, and the second layer. A second through via extends through the third layer and the fourth layer. A bottom surface of the second through via contacts a top surface of the first through via.

公开(公告)号：US12266579B2

公开(公告)日：2025-04-01

申请号：US17461004

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chan Li ,  Sheng-Chau Chen ,  Cheng-Hsien Chou ,  Cheng-Yuan Tsai

IPC: H01L21/02 ,  C23C16/46 ,  C23C16/50 ,  C23C16/52 ,  H01J37/32 ,  H01L21/66

Abstract: A thin-film deposition system includes a top plate positioned above a wafer and configured to generate a plasma during a thin-film deposition process. The system includes a gap sensor configured to generate sensor signals indicative of a gap between the wafer and the top plate. The system includes a control system configured to adjust the gap during the thin-film deposition process responsive to the sensor signals.

公开(公告)号：US12266541B2

公开(公告)日：2025-04-01

申请号：US17350206

申请日：2021-06-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-En Lin ,  Chunyao Wang

IPC: H01L21/3213 ,  H01L21/02 ,  H01L21/311

Abstract: In an embodiment, a method includes: forming a photoresist over a target layer; performing a plasma-enhanced deposition process, the plasma-enhanced deposition process etching sidewalls of the photoresist while depositing a spacer layer on the sidewalls of the photoresist; patterning the spacer layer to form spacers on the sidewalls of the photoresist; and etching the target layer using the spacers and the photoresist as a combined etching mask.

公开(公告)号：US12265334B2

公开(公告)日：2025-04-01

申请号：US18361879

申请日：2023-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Dong-Yo Jheng ,  Ken-Hsien Hsieh ,  Shih-Ming Chang ,  Chih-Jie Lee ,  Shuo-Yen Chou ,  Ru-Gun Liu

IPC: G03F1/36 ,  G03F7/00

Abstract: A method includes receiving a layout for fabricating a mask, determining a plurality of target contours corresponding to a plurality of sets of lithographic process conditions, determining a modification to the layout, simulating the modification to the layout under the plurality of sets of lithographic process conditions to produce a plurality of simulated contours, determining a cost of the modification to the layout based on comparisons between the plurality of simulated contours and corresponding ones in the plurality of target contours, and providing the modification to the layout for fabricating the mask based at least in part on the cost being within a predetermined threshold.