公开(公告)号：US06306757B1

公开(公告)日：2001-10-23

申请号：US09323890

申请日：1999-06-02

申请人： Keh-Ching Huang ,  Ming-Sheng Yang ,  Tong-Yu Chen ,  Tzu-Guey Jung

发明人： Keh-Ching Huang ,  Ming-Sheng Yang ,  Tong-Yu Chen ,  Tzu-Guey Jung

IPC分类号： H01L214763

CPC分类号： H01L21/76843 ,  H01L21/76841 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metallization method for forming multilevel interconnect is disclosed. The method includes firstly providing a first conductor layer on which there is a dielectric layer. A glue layer is then formed on the dielectric layer, followed by forming an opening from top surface of the glue layer to the first conductor layer. After forming a barrier layer on the glue layer and all surfaces in the opening, a second conductor is formed on the barrier layer and fills the opening. Subsequently, the second conductor layer and the barrier layer are removed until the glue layer exposes. A third conductor is defined on the glue layer and the second conductor. The product will solve the problem of high via resistivity caused by stripping solvent and etchant.

摘要翻译： 公开了一种用于形成多层互连的金属化方法。 该方法包括首先提供其上存在电介质层的第一导体层。 然后在电介质层上形成胶层，随后从胶层的顶表面到第一导体层形成开口。 在胶层和开口中的所有表面上形成阻挡层之后，在阻挡层上形成第二导体并填充开口。 随后，去除第二导体层和阻挡层，直到胶层露出。 第三导体被限定在胶层和第二导体上。 该产品将解决由剥离溶剂和蚀刻剂引起的高电阻率的问题。

公开(公告)号：US06218084B1

公开(公告)日：2001-04-17

申请号：US09212727

申请日：1998-12-15

申请人： Chan-Lon Yang ,  Tong-Yu Chen ,  Michael W C Huang

发明人： Chan-Lon Yang ,  Tong-Yu Chen ,  Michael W C Huang

IPC分类号： G03F742

CPC分类号： H01L21/31138 ,  G03F7/427 ,  H01L21/31116

摘要： A method described for removing a photoresist/polymers layer on a substrate. The method comprises the steps of providing a wafer having an oxide layer, a photoresist/polymers layer, an opening penetrating through the photoresist/polymers layer and the oxide layer, and the sidewall polymer on the surface of photoresist layer and the oxide layer. An in-situ plasma-etching step using an additional gas mixed with oxygen as source is performed to remove the photoresist/polymers layer without residues, no damages to substrate and oxide and no changes on the critical dimension of the opening during etching step.

公开(公告)号：US06184147B2

公开(公告)日：2001-02-06

申请号：US09263421

申请日：1999-03-05

申请人： Chan-Lon Yang ,  Tong-Yu Chen ,  Keh-Ching Huang

发明人： Chan-Lon Yang ,  Tong-Yu Chen ,  Keh-Ching Huang

IPC分类号： H01L21302

CPC分类号： H01L21/76897 ,  H01J37/32082 ,  H01J2237/3347 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802

摘要： A method for forming a high aspect ration (HAR>4:1) borderless contact hole is described. The method forms a contact/via hole in the silicon oxide layer by performing an etching process with an etchant, C4F8/C2F6,/Ar/CO or C4F8/Ar/CO, on an etcher. The etcher includes a ring, a roof, a chiller and a chamber. The etchant used in the etching process is controlled under conditions including a C4F8 flow of about 10 to 20 sccm, a CO flow of about 1 to 100 sccm, and an Ar flow of about 100 to 500 sccm. The flow of C2F6 is about 0.5 to 1.5 times that of C4F8. The conditions of the etcher include a roof temperature of about 150 to 300° C., a chiller temperature of about −20 to 20° C., a wall temperature of about 150 to 400° C., a ring temperature of about 150 to 400° C., and a pressure within the chamber of about 4 to 50 mtorr. By controlling the chamber pressure and the deposition rate of the polymer molecules, a properly profiled contact hole is obtained.

摘要翻译： 描述了形成高纵横比（HAR> 4:1）无边界接触孔的方法。 该方法通过在蚀刻剂上用蚀刻剂C 4 F 8 / C 2 F 6，/ Ar / CO或C 4 F 8 / Ar / CO执行蚀刻处理来形成氧化硅层中的接触/通孔。 蚀刻器包括环，屋顶，冷却器和室。 在蚀刻工艺中使用的蚀刻剂在约10至20sccm的C 4 F 8流量，约1至100sccm的CO流量和约100至500sccm的Ar流量的条件下进行控制。 C2F6的流量约为C4F8的0.5〜1.5倍。 蚀刻器的条件包括约150至300℃的屋顶温度，约-20至20℃的冷却器温度，约150至400℃的壁温度，约150至400℃的环境温度 400℃，室内的压力为约4至50毫托。 通过控制室压力和聚合物分子的沉积速率，获得适当的异型接触孔。

公开(公告)号：US06184142B2

公开(公告)日：2001-02-06

申请号：US09302204

申请日：1999-04-26

申请人： Hsien-Ta Chung ,  Chan-Lon Yang ,  Tong-Yu Chen ,  Tri-Rung Yew

发明人： Hsien-Ta Chung ,  Chan-Lon Yang ,  Tong-Yu Chen ,  Tri-Rung Yew

IPC分类号： H01L2100

CPC分类号： H01L21/76807 ,  H01L21/31144 ,  H01L21/76802

摘要： A simplified method is disclosed for etching low k organic dielectric film. A substrate is provided with a hardmask layer and low k organic dielectric layer formed thereon in which hardmask layer is on the dielectric layer. A layer of photoresist is formed on the hardmask layer and imaged with a pattern by exposure through a dark field mask. As a key step, the pattern is transferred into the hardmask layer by dry etching and then the photoresist is stripped in-situ. Then, the interconnect is formed by using dry etching the low k organic dielectric layer using the hardmask layer as a mask, and readying it for the next semiconductor process.

摘要翻译： 公开了一种用于蚀刻低k有机介电膜的简化方法。 衬底上设置有硬掩模层和形成在其上的低k有机介电层，其中硬掩模层位于电介质层上。 在硬掩模层上形成光致抗蚀剂层，并通过暗场掩模曝光以图案成像。 作为关键步骤，通过干蚀刻将图案转移到硬掩模层中，然后原位剥离光致抗蚀剂。 然后，通过使用硬掩模层作为掩模使用干式蚀刻低k有机介电层形成互连，并将其准备用于下一个半导体工艺。

公开(公告)号：US06180532B2

公开(公告)日：2001-01-30

申请号：US09213129

申请日：1998-12-15

申请人： Chan-Lon Yang ,  Tong-Yu Chen ,  Tsu-An Lin

发明人： Chan-Lon Yang ,  Tong-Yu Chen ,  Tsu-An Lin

IPC分类号： H01L213065

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  H01L21/31144

摘要： A method for forming a contact hole in a silicon oxide layer formed over a silicon nitride layer and a substrate performs an etching process with an etchant, C4F8/Ar or C4F8/C2F6/Ar, on an inductively coupled plasma etcher. The inductively coupled plasma etcher contains a chamber, a ring, and a roof. The etchant used in the etching process is controlled by conditions that include a C4F8 flow of about 10 to 20 sccm, a CO flow of less than about 100 sccm, and an Ar flow of about 50 to 500 sccm. In the meantime, the conditions of the inductively coupled plasma etcher include a roof temperature of about 150 to 300 ° C., a ring temperature of about 150 to 400 ° C., and a pressure within the chamber of about 4 to 50 mtorr. By performing a plasma etching process under the foregoing conditions, a properly profiled contact hole is obtained.

摘要翻译： 在形成在氮化硅层和基板上的氧化硅层中形成接触孔的方法在电感耦合等离子体蚀刻器上用蚀刻剂C4F8 / Ar或C4F8 / C2F6 / Ar进行蚀刻处理。 电感耦合等离子体蚀刻器包含一个室，一个环和一个屋顶。 在蚀刻工艺中使用的蚀刻剂由包括约10至20sccm的C 4 F 8流量，小于约100sccm的CO流量和约50至500sccm的Ar流量的条件控制。 同时，电感耦合等离子体蚀刻器的条件包括约150-300℃的屋顶温度，约150-400℃的环境温度和室内压力为约4-50mtorr。 通过在上述条件下进行等离子体蚀刻工艺，可以获得适当的异型接触孔。

公开(公告)号：US6147007A

公开(公告)日：2000-11-14

申请号：US330597

申请日：1999-06-11

申请人： Chan-Lon Yang ,  Wei-Che Huang ,  Tong-Yu Chen

发明人： Chan-Lon Yang ,  Wei-Che Huang ,  Tong-Yu Chen

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/00

CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76814

摘要： The present invention relates to a method of forming a contact hole on the semiconductor wafer. The semiconductor wafer comprises, in ascending order, a substrate, a silicon nitride layer, a silicon oxide layer, and a photo-resist layer. There is a hole in the photo-resist layer. The method comprises: (1) performing a first anisotropic etching process in a downward direction to remove the silicon oxide layer under the hole down to the surface of the silicon nitride layer to form a recess; (2) performing an in-situ plasma cleaning process to entirely remove the polymer material remaining at the bottom of the recess; (3) performing an in-situ second anisotropic etching process in a downward direction to remove the silicon nitride layer from the bottom of the recess down to the surface of the substrate to form the contact hole; (4) performing another in-situ cleaning process to entirely remove the polymer material remaining at the bottom of the contact hole.

摘要翻译： 本发明涉及在半导体晶片上形成接触孔的方法。 半导体晶片按照升序包括衬底，氮化硅层，氧化硅层和光致抗蚀剂层。 光致抗蚀剂层中有一个孔。 该方法包括：（1）沿向下的方向进行第一各向异性蚀刻处理，以将氧化硅层下面的氮化硅层的表面去除，形成凹部; （2）进行原位等离子体清洗工艺以完全除去残留在凹部底部的聚合物材料; （3）在向下的方向上进行原位第二各向异性蚀刻工艺，以将氮化硅层从凹槽的底部向下移动到衬底的表面，以形成接触孔; （4）进行另一原位清洗处理以完全除去留在接触孔底部的聚合物材料。

公开(公告)号：US09006107B2

公开(公告)日：2015-04-14

申请号：US13417299

申请日：2012-03-11

申请人： Chih-Jung Wang ,  Tong-Yu Chen

发明人： Chih-Jung Wang ,  Tong-Yu Chen

IPC分类号： H01L21/311 ,  H01L21/033

CPC分类号： H01L27/11 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28123 ,  H01L21/3213 ,  H01L21/823431 ,  H01L21/845

摘要： A method for fabricating a patterned structure in a semiconductor device is provided. First, a substrate with a first region and a second region is provided. Then, a plurality of sacrificial patterns is respectively formed within the first region and the second region. A first spacer is then formed on the sidewalls of each of the sacrificial patterns followed by forming a mask layer to cover the sacrificial patterns located within the first region. Finally, the first spacer exposed from the mask layer is trimmed to be a second spacer and the mask layer is then removed.

摘要翻译： 提供了一种在半导体器件中制造图案化结构的方法。 首先，提供具有第一区域和第二区域的基板。 然后，分别在第一区域和第二区域内形成多个牺牲图案。 然后在每个牺牲图案的侧壁上形成第一间隔物，随后形成掩模层以覆盖位于第一区域内的牺牲图案。 最后，将从掩模层露出的第一间隔物修剪成第二间隔物，然后除去掩模层。

公开(公告)号：US20130252431A1

公开(公告)日：2013-09-26

申请号：US13426624

申请日：2012-03-22

申请人： Tong-Yu Chen ,  Chih-Jung Wang

发明人： Tong-Yu Chen ,  Chih-Jung Wang

IPC分类号： H01L21/311

CPC分类号： H01L21/76807 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28132 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/31144 ,  H01L29/66795

摘要： The present invention provides a method of forming a trench in a semiconductor substrate. First, a first patterned mask layer is formed on a semiconductor substrate. The first patterned mask layer has a first trench. Then, a material layer is formed along the first trench. Then, a second patterned mask layer is formed on the material layer to completely fill the first trench. A part of the material layer is removed when the portion of the material layer between the second patterned mask layer and the semiconductor substrate is maintained so as to form a second trench. Lastly, an etching process is performed by using the first patterned mask layer and the second patterned mask layer as a mask.

公开(公告)号：US20130122673A1

公开(公告)日：2013-05-16

申请号：US13293125

申请日：2011-11-10

申请人： Chih-Jung Wang ,  Tong-Yu Chen

发明人： Chih-Jung Wang ,  Tong-Yu Chen

IPC分类号： H01L21/8234

CPC分类号： H01L21/823431 ,  H01L29/66795

摘要： A method of fabricating a double-gate transistor and a tri-gate transistor on a common substrate, in which, a substrate includes a first fin structure covered with a first mask layer and a second fin structure covered with a second mask layer, the first mask layer is removed, a gate material layer is formed and covers the first fin structure and the second mask layer, the gate material layer is patterned to result in a tri-gate structure covering the first fin structure and a double-gate structure covering the second fin structure and the second mask layer, and a source and a drain are formed in each of these two fin structures each at two sides of the gates.

摘要翻译： 一种在公共衬底上制造双栅晶体管和三栅极晶体管的方法，其中衬底包括被第一掩模层覆盖的第一鳍结构和被第二掩模层覆盖的第二鳍结构， 去除掩模层，形成栅极材料层并覆盖第一鳍结构和第二掩模层，对栅极材料层进行构图以形成覆盖第一鳍结构的三栅结构和覆盖第一鳍结构的双栅结构 第二鳍结构和第二掩模层，并且在这两个鳍结构中的每一个中在栅极的两侧形成源极和漏极。

公开(公告)号：US08426283B1

公开(公告)日：2013-04-23

申请号：US13293125

申请日：2011-11-10

申请人： Chih-Jung Wang ,  Tong-Yu Chen

发明人： Chih-Jung Wang ,  Tong-Yu Chen

IPC分类号： H01L21/336 ,  H01L21/02

CPC分类号： H01L21/823431 ,  H01L29/66795

摘要： A method of fabricating a double-gate transistor and a tri-gate transistor on a common substrate, in which, a substrate includes a first fin structure covered with a first mask layer and a second fin structure covered with a second mask layer, the first mask layer is removed, a gate material layer is formed and covers the first fin structure and the second mask layer, the gate material layer is patterned to result in a tri-gate structure covering the first fin structure and a double-gate structure covering the second fin structure and the second mask layer, and a source and a drain are formed in each of these two fin structures each at two sides of the gates.

摘要翻译： 一种在公共衬底上制造双栅晶体管和三栅极晶体管的方法，其中衬底包括被第一掩模层覆盖的第一鳍结构和被第二掩模层覆盖的第二鳍结构， 去除掩模层，形成栅极材料层并覆盖第一鳍结构和第二掩模层，对栅极材料层进行构图以形成覆盖第一鳍结构的三栅结构和覆盖第一鳍结构的双栅结构 第二鳍结构和第二掩模层，并且在这两个鳍结构中的每一个中在栅极的两侧形成源极和漏极。