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    Fin-type field effect transistor
    1.
    发明授权
    Fin-type field effect transistor 有权
    鳍型场效应晶体管

    公开(公告)号：US08803247B2

    公开(公告)日：2014-08-12

    申请号：US13326429

    申请日：2011-12-15

    申请人： Chih-Jung Wang ,  Tong-Yu Chen

    发明人： Chih-Jung Wang ,  Tong-Yu Chen

    IPC分类号： H01L27/148 ,  H01L29/66 ,  H01L29/00 ,  H01L27/088 ,  H01L21/339 ,  H01L21/00 ,  H01L21/84 ,  H01L21/338 ,  H01L21/337 ,  H01L21/336 ,  H01L21/8234

    CPC分类号： H01L27/1211 ,  H01L21/845

    摘要： A fin-type field effect transistor including at least one fin-type semiconductor structure, a gate strip and a gate insulating layer is provided. The fin-type semiconductor structure is doped with a first type dopant and has a block region with a first doping concentration and a channel region with a second doping concentration. The first doping concentration is larger than the second doping concentration. The blocking region has a height. The channel region is configured above the blocking region. The gate strip is substantially perpendicular to the fin-type semiconductor structure and covers above the channel region. The gate insulating layer is disposed between the gate strip and the fin-type semiconductor structure.

    摘要翻译： 提供了包括至少一个鳍式半导体结构，栅极条和栅极绝缘层的鳍式场效应晶体管。 翅片型半导体结构掺杂有第一种掺杂剂并具有具有第一掺杂浓度的阻挡区和具有第二掺杂浓度的沟道区。 第一掺杂浓度大于第二掺杂浓度。 阻挡区域具有高度。 通道区域被配置在阻塞区域之上。 栅极条基本上垂直于鳍状半导体结构并且覆盖在沟道区域上方。 栅极绝缘层设置在栅极条和鳍状半导体结构之间。

    Field effect transistor and manufacturing method thereof
    3.
    发明授权
    Field effect transistor and manufacturing method thereof 有权
    场效应晶体管及其制造方法

    公开(公告)号：US09012975B2

    公开(公告)日：2015-04-21

    申请号：US13517759

    申请日：2012-06-14

    申请人： Tong-Yu Chen ,  Chih-Jung Wang

    发明人： Tong-Yu Chen ,  Chih-Jung Wang

    IPC分类号： H01L29/792 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L29/423

    CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/42344 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/792

    摘要： A field effect transistor (FET) and a manufacturing method thereof are provided. The FET includes a substrate, a fin bump, an insulating layer, a charge trapping structure and a gate structure. The fin bump is disposed on the substrate. The insulating layer is disposed on the substrate and located at two sides of the fin bump. The charge trapping structure is disposed on the insulating layer and located at at least one side of the fin bump. A cross-section of the charge trapping structure is L-shaped. The gate structure covers the fin bump and the charge trapping structure.

    摘要翻译： 提供场效应晶体管（FET）及其制造方法。 FET包括衬底，鳍片凸块，绝缘层，电荷俘获结构和栅极结构。 翅片凸块设置在基板上。 绝缘层设置在基板上并且位于散热片凸块的两侧。 电荷捕获结构设置在绝缘层上并位于散热片凸块的至少一侧。 电荷捕获结构的横截面为L形。 栅极结构覆盖鳍片凸起和电荷俘获结构。

    Method of forming trench in semiconductor substrate
    4.
    发明授权
    Method of forming trench in semiconductor substrate 有权
    在半导体衬底中形成沟槽的方法

    公开(公告)号：US08946078B2

    公开(公告)日：2015-02-03

    申请号：US13426624

    申请日：2012-03-22

    申请人： Tong-Yu Chen ,  Chih-Jung Wang

    发明人： Tong-Yu Chen ,  Chih-Jung Wang

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76807 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28132 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/31144 ,  H01L29/66795

    摘要： The present invention provides a method of forming a trench in a semiconductor substrate. First, a first patterned mask layer is formed on a semiconductor substrate. The first patterned mask layer has a first trench. Then, a material layer is formed along the first trench. Then, a second patterned mask layer is formed on the material layer to completely fill the first trench. A part of the material layer is removed when the portion of the material layer between the second patterned mask layer and the semiconductor substrate is maintained so as to form a second trench. Lastly, an etching process is performed by using the first patterned mask layer and the second patterned mask layer as a mask.

    摘要翻译： 本发明提供一种在半导体衬底中形成沟槽的方法。 首先，在半导体衬底上形成第一图案化掩模层。 第一图案化掩模层具有第一沟槽。 然后，沿着第一沟槽形成材料层。 然后，在材料层上形成第二图案化掩模层以完全填充第一沟槽。 当保持第二图案化掩模层和半导体衬底之间的材料层的部分以形成第二沟槽时，去除材料层的一部分。 最后，通过使用第一图案化掩模层和第二图案化掩模层作为掩模来执行蚀刻工艺。

    PATTERNED STRUCTURE OF SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF
    5.
    发明申请
    PATTERNED STRUCTURE OF SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF 有权
    半导体器件的图形结构及其制作方法

    公开(公告)号：US20130234301A1

    公开(公告)日：2013-09-12

    申请号：US13417299

    申请日：2012-03-11

    申请人： Chih-Jung Wang ,  Tong-Yu Chen

    发明人： Chih-Jung Wang ,  Tong-Yu Chen

    IPC分类号： H01L29/02 ,  H01L21/32

    CPC分类号： H01L27/11 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28123 ,  H01L21/3213 ,  H01L21/823431 ,  H01L21/845

    摘要： A method for fabricating a patterned structure in a semiconductor device is provided. First, a substrate with a first region and a second region is provided. Then, a plurality of sacrificial patterns is respectively formed within the first region and the second region. A first spacer is then formed on the sidewalls of each of the sacrificial patterns followed by forming a mask layer to cover the sacrificial patterns located within the first region. Finally, the first spacer exposed from the mask layer is trimmed to be a second spacer and the mask layer is then removed.

    摘要翻译： 提供了一种在半导体器件中制造图案化结构的方法。 首先，提供具有第一区域和第二区域的基板。 然后，分别在第一区域和第二区域内形成多个牺牲图案。 然后在每个牺牲图案的侧壁上形成第一间隔物，随后形成掩模层以覆盖位于第一区域内的牺牲图案。 最后，将从掩模层露出的第一间隔物修剪成第二间隔物，然后除去掩模层。

    FINFET STRUCTURE AND METHOD FOR MAKING THE SAME
    6.
    发明申请
    FINFET STRUCTURE AND METHOD FOR MAKING THE SAME 有权
    FINFET结构及其制造方法

    公开(公告)号：US20130175621A1

    公开(公告)日：2013-07-11

    申请号：US13347707

    申请日：2012-01-11

    申请人： Tong-Yu Chen ,  Chih-Jung Wang

    发明人： Tong-Yu Chen ,  Chih-Jung Wang

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/786

    CPC分类号： H01L29/785 ,  H01L29/66787 ,  H01L29/7843

    摘要： A finFET device includes a substrate, at least a first fin structure disposed on the substrate, a L-shaped insulator surrounding the first fin structure and exposing, at least partially, the sidewalls of the first fin structure, wherein the height of the L-shaped insulator is inferior to the height of the first fin structure in order to expose parts of the sidewalls surface of the first fin structure, and a gate structure disposed partially on the L-shaped insulator and partially on the first fin structure.

    摘要翻译： finFET器件包括衬底，至少设置在衬底上的第一鳍结构，围绕第一鳍结构并且至少部分地暴露第一鳍结构的侧壁的L形绝缘体，其中， 为了露出第一鳍片结构的侧壁表面的部分，以及部分地设置在L形绝缘体上并部分地设置在第一鳍片结构上的栅极结构，第一翅片结构的高度劣于第一翅片结构的高度。

    Method of fabricating field effect transistor with fin structure and field effect transistor with fin structure fabricated therefrom
    7.
    发明申请
    Method of fabricating field effect transistor with fin structure and field effect transistor with fin structure fabricated therefrom 有权
    具有翅片结构的场效应晶体管和由其制造的鳍结构的场效应晶体管的方法

    公开(公告)号：US20130105867A1

    公开(公告)日：2013-05-02

    申请号：US13284987

    申请日：2011-10-31

    申请人： Chih-Jung Wang ,  Tong-Yu Chen

    发明人： Chih-Jung Wang ,  Tong-Yu Chen

    IPC分类号： H01L21/336 ,  H01L29/78

    CPC分类号： H01L29/7851 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66818

    摘要： A method of fabricating a field effect transistor with a fin structure is described. At least a fin structure is formed on a substrate. A planar insulation layer covering the fin structure is formed. A trench is formed in the insulation layer and intersects the fin structure both lengthwise, and thereby an upper portion of the fin structure is exposed to the trench. The exposed upper portion of the fin structure will serve as a gate channel region. A gate structure covering the upper portion is formed within the trench. The upper portion of the fin structure may be further trimmed. Accordingly, the present invention also relates to a field effect transistor with a fin structure, in which, the channel width is less than the source/drain width, and a gate structure has two sidewalls contacting two opposite sidewalls of a source region and a drain region, respectively.

    摘要翻译： 描述了制造具有翅片结构的场效应晶体管的方法。 至少在基板上形成翅片结构。 形成覆盖翅片结构的平面绝缘层。 在绝缘层中形成沟槽，并且纵向地与鳍状结构相交，从而翅片结构的上部暴露于沟槽。 鳍结构的暴露的上部将用作栅极沟道区。 在沟槽内形成覆盖上部的栅极结构。 翅片结构的上部可以进一步修整。 因此，本发明还涉及具有翅片结构的场效应晶体管，其中沟道宽度小于源极/漏极宽度，并且栅极结构具有接触源极区域和漏极的两个相对侧壁的两个侧壁 区域。

    Patterned structure of semiconductor device and fabricating method thereof
    9.
    发明授权
    Patterned structure of semiconductor device and fabricating method thereof 有权
    半导体器件的图案化结构及其制造方法

    公开(公告)号：US09006107B2

    公开(公告)日：2015-04-14

    申请号：US13417299

    申请日：2012-03-11

    申请人： Chih-Jung Wang ,  Tong-Yu Chen

    发明人： Chih-Jung Wang ,  Tong-Yu Chen

    IPC分类号： H01L21/311 ,  H01L21/033

    CPC分类号： H01L27/11 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28123 ,  H01L21/3213 ,  H01L21/823431 ,  H01L21/845

    摘要： A method for fabricating a patterned structure in a semiconductor device is provided. First, a substrate with a first region and a second region is provided. Then, a plurality of sacrificial patterns is respectively formed within the first region and the second region. A first spacer is then formed on the sidewalls of each of the sacrificial patterns followed by forming a mask layer to cover the sacrificial patterns located within the first region. Finally, the first spacer exposed from the mask layer is trimmed to be a second spacer and the mask layer is then removed.

    摘要翻译： 提供了一种在半导体器件中制造图案化结构的方法。 首先，提供具有第一区域和第二区域的基板。 然后，分别在第一区域和第二区域内形成多个牺牲图案。 然后在每个牺牲图案的侧壁上形成第一间隔物，随后形成掩模层以覆盖位于第一区域内的牺牲图案。 最后，将从掩模层露出的第一间隔物修剪成第二间隔物，然后除去掩模层。