公开(公告)号：US09397729B2

公开(公告)日：2016-07-19

申请号：US12946072

申请日：2010-11-15

Applicant: Tzu-Jin Yeh ,  Hsieh-Hung Hsieh ,  Jun-De Jin ,  Ming Hsien Tsai ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

Inventor： Tzu-Jin Yeh ,  Hsieh-Hung Hsieh ,  Jun-De Jin ,  Ming Hsien Tsai ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

IPC: H04B5/00

CPC classification number: H04B5/0081

Abstract: Through-chip coupling is utilized for signal transport, where an interface is formed between a first coil on a first integrated circuit (IC) chip and a second coil on a second IC chip. The first coil is coupled to an antenna. The second coil is coupled to an amplifier circuit. The second coil is not in direct contact with the first coil. The first coil and the second coil communicatively transmit signals between the antenna and the first amplifier circuit.

Abstract translation: 芯片耦合用于信号传输，其中在第一集成电路（IC）芯片上的第一线圈和第二IC芯片上的第二线圈之间形成接口。 第一线圈耦合到天线。 第二线圈耦合到放大器电路。 第二线圈不与第一线圈直接接触。 第一线圈和第二线圈在天线和第一放大器电路之间通信地传送信号。

公开(公告)号：US09093977B2

公开(公告)日：2015-07-28

申请号：US13562571

申请日：2012-07-31

Applicant: Jun-De Jin ,  Ming Hsien Tsai ,  Tzu-Jin Yeh

Inventor： Jun-De Jin ,  Ming Hsien Tsai ,  Tzu-Jin Yeh

IPC: H02H9/00 ,  H03H7/40 ,  H02H9/04 ,  H01L23/60 ,  H01L23/64 ,  H01L23/522

CPC classification number: H03H7/40 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/60 ,  H01L23/64 ,  H01L2924/0002 ,  H02H9/04 ,  H02H9/046 ,  Y10T29/49117 ,  H01L2924/00

Abstract: The present disclosure relates to an on-chip electrostatic discharge (ESD) protection circuit that may be reused for a variety of integrated circuit (IC) applications. Both inductor-capacitor (LC) parallel resonator and shunt inductor (connected to ground) are used as ESD protection circuits and also as a part of an impedance matching network for a given IC application. The ESD LC resonator can be designed with a variety of band pass filter (BPF) topologies. On-chip ESD protection circuit allows for co-optimization ESD and BPF performance simultaneously, a fully on-chip ESD solution for integrated passive device (IPD) processes, eliminates a need for active ESD device protection, additional processes to support off-chip ESD protection, reduces power consumption, and creates a reusable BPF topology.

Abstract translation: 本公开涉及可以重用于各种集成电路（IC）应用的片上静电放电（ESD）保护电路。 电感 - 电容（LC）并联谐振器和并联电感（连接到地）均用作ESD保护电路，也可用作给定IC应用的阻抗匹配网络的一部分。 ESD LC谐振器可以设计有各种带通滤波器（BPF）拓扑。 片上ESD保护电路允许同时优化ESD和BPF性能，用于集成无源器件（IPD）工艺的完全片上ESD解决方案，无需主动ESD器件保护，另外还支持片外ESD保护 保护，降低功耗，并创建可重用的BPF拓扑。

公开(公告)号：US20140184275A1

公开(公告)日：2014-07-03

申请号：US13753995

申请日：2013-01-30

Applicant: Tzu-Jin YEH ,  Chewn-Pu JOU ,  Jun-De JIN

Inventor： Tzu-Jin YEH ,  Chewn-Pu JOU ,  Jun-De JIN

IPC: H01L27/06 ,  H03K17/06 ,  H01L29/66

CPC classification number: H01L27/0629 ,  H01L29/0653 ,  H01L29/1087 ,  H01L29/66484 ,  H01L29/66636 ,  H01L29/7832 ,  H03K17/102 ,  H03K2217/0018

Abstract: A power cell including an isolation region having a first dopant type formed in a substrate. The power cell further includes a bottom gate having a second dopant type different from the first dopant type formed on the isolation region and a channel layer having the first dopant type formed on the bottom gate. The power cell further includes source/drain regions having the first dopant type formed in the channel layer and a first well region having the second dopant type formed around the channel layer and the source/drain regions, and the first well region electrically connected to the bottom gate. The power cell further includes a second well region having the first dopant type formed around the channel layer and contacting the isolation region and a gate structure formed on the channel layer.

Abstract translation: 一种功率单元，包括形成在基板中的具有第一掺杂剂类型的隔离区域。 功率单元还包括具有不同于在隔离区上形成的第一掺杂剂类型的第二掺杂剂型的底栅和在底栅上形成的具有第一掺杂剂类型的沟道层。 功率单元还包括在沟道层中形成的具有第一掺杂剂类型的源极/漏极区域和形成在沟道层和源极/漏极区域周围的具有第二掺杂剂类型的第一阱区域，以及与第一阱区域电连接的第一阱区域 底门 功率单元还包括具有第一掺杂剂类型的第二阱区，该第二阱区形成在沟道层周围并与隔离区接触并形成在沟道层上的栅极结构。

公开(公告)号：US20140183660A1

公开(公告)日：2014-07-03

申请号：US13731873

申请日：2012-12-31

Applicant: Chewn-Pu JOU ,  Tzu-Jin YEH ,  Chia-Chung CHEN

Inventor： Chewn-Pu JOU ,  Tzu-Jin YEH ,  Chia-Chung CHEN

IPC: H01L29/78

CPC classification number: H01L29/785 ,  H01L29/66901

Abstract: A power cell includes a fin over a substrate, the fin extending in a direction substantially perpendicular to a bottom surface of the substrate. The fin includes a first dopant type. The power cell further includes at least one isolation region over the substrate between the fin and an adjacent fin. The power cell further includes a gate structure in contact with the fin and the at least one isolation region, wherein the gate structure comprises a doped region in the fin, wherein the doped region has a second dopant type different from the first dopant type and the doped region defines a channel region in the fin.

Abstract translation: 功率单元包括在衬底上的翅片，翅片沿基本上垂直于衬底的底表面的方向延伸。 散热片包括第一掺杂剂类型。 功率单元还包括在鳍片和相邻鳍片之间的衬底上的至少一个隔离区域。 所述功率单元还包括与所述鳍片和所述至少一个隔离区域接触的栅极结构，其中所述栅极结构包括所述鳍片中的掺杂区域，其中所述掺杂区域具有不同于所述第一掺杂剂类型的第二掺杂剂类型， 掺杂区域限定鳍片中的沟道区域。

公开(公告)号：US08729968B2

公开(公告)日：2014-05-20

申请号：US13103571

申请日：2011-05-09

Applicant: Hsieh-Hung Hsieh ,  Ming Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

Inventor： Hsieh-Hung Hsieh ,  Ming Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

IPC: H03L5/00

CPC classification number: G01R31/2824

Abstract: A built-in self-test circuit for testing a voltage controlled oscillator comprises a voltage controlled oscillator, a buffer having an input coupled to an output of the voltage controlled oscillator and a radio frequency peak detector coupled to the output of the buffer. The radio frequency peak detector is configured to receive an ac signal from the voltage controlled oscillator and generate a dc value proportional to the ac signal at an output of the radio frequency peak detector. Furthermore, the output of the radio frequency peak detector generates a dc value proportional to an amplitude of the ac signal from the voltage controlled oscillator when the voltage controlled oscillator functions correctly. On the other hand, the output of the radio frequency peak detector is at zero volts when the voltage controlled oscillator fails to generate an ac signal.

Abstract translation: 用于测试压控振荡器的内置自检电路包括压控振荡器，具有耦合到压控振荡器的输出的输入的缓冲器和耦合到缓冲器的输出的射频峰值检测器。 射频峰值检测器被配置为从压控振荡器接收交流信号，并且在射频峰值检测器的输出处产生与ac信号成比例的直流值。 此外，当压控振荡器正常工作时，射频峰值检测器的输出产生与来自压控振荡器的ac信号的幅度成比例的直流值。 另一方面，当压控振荡器不能产生交流信号时，射频峰值检测器的输出为零伏特。

公开(公告)号：US08664729B2

公开(公告)日：2014-03-04

申请号：US13325922

申请日：2011-12-14

Applicant: Chewn-Pu Jou ,  Tzu-Jin Yeh ,  Hsieh-Hung Hsieh

Inventor： Chewn-Pu Jou ,  Tzu-Jin Yeh ,  Hsieh-Hung Hsieh

IPC: H01L27/088

CPC classification number: H01L29/66795 ,  H01L29/42372 ,  H01L29/785

Abstract: Methods and apparatus for reduced gate resistance finFET. A metal gate transistor structure is disclosed including a plurality of semiconductor fins formed over a semiconductor substrate, the fins being arranged in parallel and spaced apart; a metal containing gate electrode formed over the semiconductor substrate and overlying a channel gate region of each of the semiconductor fins, and extending over the semiconductor substrate between the semiconductor fins; an interlevel dielectric layer overlying the gate electrode and the semiconductor substrate; and a plurality of contacts disposed in the interlevel dielectric layer and extending through the interlevel dielectric layer to the gate electrode; a low resistance metal strap formed over the interlevel dielectric layer and coupled to the gate electrode by the plurality of contacts; wherein the plurality of contacts are spaced apart from the channel gate regions of the semiconductor fins. Methods for forming the reduced gate finFET are disclosed.

Abstract translation: 降低栅极电阻finFET的方法和装置。 公开了一种金属栅极晶体管结构，其包括形成在半导体衬底上的多个半导体鳍片，所述鳍片平行布置并间隔开; 一个含金属的栅电极，形成在半导体衬底之上，并且覆盖每个半导体鳍片的沟道栅极区域，并且在半导体鳍片之间的半导体衬底上延伸; 覆盖所述栅电极和所述半导体衬底的层间电介质层; 以及多个触点，其布置在所述层间电介质层中并且延伸穿过所述层间电介质层到所述栅电极; 形成在所述层间电介质层上并且由所述多个触点耦合到所述栅电极的低电阻金属带; 其中所述多个触点与所述半导体鳍片的沟道栅极区域间隔开。 公开了形成栅极finFET的方法。

公开(公告)号：US20130241634A1

公开(公告)日：2013-09-19

申请号：US13419911

申请日：2012-03-14

Applicant: Hsieh-Hung HSIEH ,  Yi-Hsuan LIU ,  Tzu-Jin YEH ,  Chewn-Pu JOU ,  Fu-Lung HSUEH

Inventor： Hsieh-Hung HSIEH ,  Yi-Hsuan LIU ,  Tzu-Jin YEH ,  Chewn-Pu JOU ,  Fu-Lung HSUEH

IPC: H01L25/00

CPC classification number: H01L23/48 ,  H01L23/66 ,  H01L25/0657 ,  H01L2225/06531 ,  H01L2924/0002 ,  H04B5/0075 ,  H01L2924/00

Abstract: An integrated circuit includes a first chip and a second chip coupled to the first chip in a vertical stack. The first chip includes a radio frequency circuit and a first coil electrically coupled to the radio frequency circuit. The second chip includes a calibration circuit and a second coil electrically coupled to the calibration circuit. The calibration circuit is configured to calibrate the radio frequency circuit disposed on the first chip through inductive coupling between the first and second coils.

Abstract translation: 集成电路包括在垂直堆叠中耦合到第一芯片的第一芯片和第二芯片。 第一芯片包括射频电路和电耦合到射频电路的第一线圈。 第二芯片包括校准电路和电耦合到校准电路的第二线圈。 校准电路被配置为通过第一和第二线圈之间的感应耦合来校准设置在第一芯片上的射频电路。

公开(公告)号：US20130207230A1

公开(公告)日：2013-08-15

申请号：US13372873

申请日：2012-02-14

Applicant: Jun-De Jin ,  Tzu-Jin Yeh

Inventor： Jun-De Jin ,  Tzu-Jin Yeh

IPC: H01L27/06 ,  H01L21/02

CPC classification number: H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure having an in situ chip-level ferrite bead inductor and method for forming the same. Embodiments include a substrate, a first dielectric layer formed on the substrate, a lower ferrite layer formed on the first dielectric layer, and an upper ferrite layer spaced apart from the lower ferrite layer in the structure. A first metal layer may be formed above the lower ferrite layer and a second metal layer formed below the upper ferrite layer, wherein at least the first or second metal layer has a coil configuration including multiple turns. At least one second dielectric layer may be disposed between the first and second metal layers. The ferrite bead inductor has a small form factor and is amenable to formation using BEOL processes.

Abstract translation: 一种具有原位芯片级铁氧体磁珠电感器的半导体结构及其形成方法。 实施例包括基板，形成在基板上的第一介电层，形成在第一介电层上的下铁氧体层，以及与该结构中的下铁氧体层间隔开的上铁氧体层。 第一金属层可以形成在下铁素体层上方，第二金属层形成在上铁氧体层下面，其中至少第一或第二金属层具有包括多匝的线圈构型。 至少一个第二电介质层可以设置在第一和第二金属层之间。 铁氧体磁珠电感器具有小的外形尺寸，并且可以使用BEOL工艺来形成。

公开(公告)号：US20130154011A1

公开(公告)日：2013-06-20

申请号：US13325922

申请日：2011-12-14

Applicant: Chewn-Pu Jou ,  Tzu-Jin Yeh ,  Hsieh-Hung Hsieh

Inventor： Chewn-Pu Jou ,  Tzu-Jin Yeh ,  Hsieh-Hung Hsieh

IPC: H01L27/088 ,  H01L21/336

CPC classification number: H01L29/66795 ,  H01L29/42372 ,  H01L29/785

Abstract: Methods and apparatus for reduced gate resistance finFET. A metal gate transistor structure is disclosed including a plurality of semiconductor fins formed over a semiconductor substrate, the fins being arranged in parallel and spaced apart; a metal containing gate electrode formed over the semiconductor substrate and overlying a channel gate region of each of the semiconductor fins, and extending over the semiconductor substrate between the semiconductor fins; an interlevel dielectric layer overlying the gate electrode and the semiconductor substrate; and a plurality of contacts disposed in the interlevel dielectric layer and extending through the interlevel dielectric layer to the gate electrode; a low resistance metal strap formed over the interlevel dielectric layer and coupled to the gate electrode by the plurality of contacts; wherein the plurality of contacts are spaced apart from the channel gate regions of the semiconductor fins. Methods for forming the reduced gate finFET are disclosed.

Abstract translation: 降低栅极电阻finFET的方法和装置。 公开了一种金属栅极晶体管结构，其包括形成在半导体衬底上的多个半导体鳍片，所述鳍片平行布置并间隔开; 一个含金属的栅电极，形成在半导体衬底之上，并且覆盖每个半导体鳍片的沟道栅极区域，并且在半导体鳍片之间的半导体衬底上延伸; 覆盖所述栅电极和所述半导体衬底的层间电介质层; 以及多个触点，其布置在所述层间电介质层中并且延伸穿过所述层间电介质层到所述栅电极; 形成在所述层间电介质层上并且由所述多个触点耦合到所述栅电极的低电阻金属带; 其中所述多个触点与所述半导体鳍片的沟道栅极区域间隔开。 公开了形成栅极finFET的方法。

公开(公告)号：US08334571B2

公开(公告)日：2012-12-18

申请号：US12731562

申请日：2010-03-25

Applicant: Ming-Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

Inventor： Ming-Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

IPC: H01L23/60 ,  H01L23/64 ,  H01L29/08

CPC classification number: H01L27/0255 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An ESD protection device includes a first well of a first semiconductor type disposed in a substrate of a second semiconductor type forming a first diode. A second well of the second semiconductor type is formed in the substrate to form a second diode with the first well. A first plurality of doped regions of the first semiconductor type are formed in an upper surface of the first well. A second plurality of doped regions of the second semiconductor type are formed in the upper surface of the first well forming a third diode with the first well. A plurality of STI regions are formed in the upper surface of the first well. Each STI region is disposed between a doped region of the first and second semiconductor types. The third diode provides a current bypass when an ESD voltage spike is received at one of the first or second plurality of doped regions.

Abstract translation: ESD保护装置包括设置在形成第一二极管的第二半导体类型的衬底中的第一半导体类型的第一阱。 第二半导体类型的第二阱形成在衬底中以与第一阱形成第二二极管。 第一半导体类型的第一多个掺杂区域形成在第一阱的上表面中。 第二半导体类型的第二多个掺杂区域形成在第一阱的上表面中，其与第一阱形成第三二极管。 多个STI区域形成在第一阱的上表面中。 每个STI区域设置在第一和第二半导体类型的掺杂区域之间。 当在第一或第二多个掺杂区域中的一个处接收ESD电压尖峰时，第三二极管提供电流旁路。