公开(公告)号：US06642105B2

公开(公告)日：2003-11-04

申请号：US10131010

申请日：2002-04-24

Applicant: Kyung-Hyun Kim ,  Chang-Ki Hong ,  U-In Chung ,  Bum-Soo Kim ,  Yoo-Cheol Shin ,  Kyu-Chan Park

Inventor： Kyung-Hyun Kim ,  Chang-Ki Hong ,  U-In Chung ,  Bum-Soo Kim ,  Yoo-Cheol Shin ,  Kyu-Chan Park

IPC: H01L21336

CPC classification number: H01L21/823462 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11541

Abstract: A semiconductor device having multi-gate insulating layers and methods of fabricating the same are provided. The semiconductor device includes an isolation region disposed at a predetermined region of a semiconductor substrate. The isolation region defines at least one first active region and at least one second active region. The first active region is covered with a first gate insulating layer, and the second active region is covered with a second gate insulating layer which is thinner than the first gate insulating layer. Preferably, the top surface of the first gate insulating layer has the same height as the that of the second gate insulating layer. The isolation region is filled with an isolation layer which preferably covers the entire sidewalls of the first and second gate insulating layers. A typical method includes the step of selectively forming a first gate insulating layer at a predetermined region of a semiconductor substrate. A second gate insulating layer which is thinner than the first insulating layer is selectively formed at the surface of the semiconductor substrate adjacent to the first gate insulating layer. Preferably, the bottom surface of the first gate insulating layer is lower than that of the second gate insulating layer. The first and second gate insulating layers are covered with a conductive layer. The conductive layer, the first and second gate insulating layers, and the substrate are etched to form an isolation region, for example, a trench region, defining a first active region under the first gate insulating layer and a second active region under the second gate insulating. An isolation layer is formed in the trench region. The isolation layer preferably covers the entire sidewalls of the first and second gate insulating layers.

公开(公告)号：US5629238A

公开(公告)日：1997-05-13

申请号：US557534

申请日：1995-11-14

Applicant: Ji-hyun Choi ,  Hong-jae Shin ,  Byung-keun Hwang ,  U-in Chung

Inventor： Ji-hyun Choi ,  Hong-jae Shin ,  Byung-keun Hwang ,  U-in Chung

IPC: H01L21/3205 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L21/283

CPC classification number: H01L21/76831 ,  H01L21/76877

Abstract: A method for forming a conductive line uses a fluorine doped oxide layer as an insulating layer between conductive lines. The method comprises the steps of: (a) forming a fluorine doped oxide layer on a semiconductor substrate on which a lower structure is formed; (b) etching the oxide layer of the region where a conductive line is to be formed, thereby forming a trench; (c) forming an insulating layer on the overall surface of the resultant substrate; depositing conductive material on the resultant substrate; and (e) etching back the conductive material so that the conductive material is left on the trench only, thereby forming a conductive line. In this method, the conductive line is formed of aluminum-containing material and the insulating layer is formed of silicon dioxide. In the present invention, the insulating layer is interposed between the fluorine doped oxide layer and the aluminum-containing conductive line and thus the conductive line is free from corrosion.

Abstract translation: 形成导线的方法使用氟掺杂氧化物层作为导线之间的绝缘层。 该方法包括以下步骤：（a）在形成下部结构的半导体衬底上形成氟掺杂氧化物层; （b）蚀刻要形成导电线的区域的氧化物层，从而形成沟槽; （c）在所得基板的整个表面上形成绝缘层; 在所得基板上沉积导电材料; 和（e）蚀刻导电材料，使得导电材料仅留在沟槽上，从而形成导电线。 在该方法中，导电线由含铝材料形成，绝缘层由二氧化硅形成。 在本发明中，绝缘层介于氟掺杂氧化物层和含铝导电线之间，因此导电线无腐蚀。

公开(公告)号：US09118795B2

公开(公告)日：2015-08-25

申请号：US12805723

申请日：2010-08-17

Applicant: Ho-jung Kim ,  U-in Chung ,  Jai-kwang Shin ,  Sun-il Kim ,  I-hun Song ,  Chang-jung Kim ,  Sang-hun Jeon

Inventor： Ho-jung Kim ,  U-in Chung ,  Jai-kwang Shin ,  Sun-il Kim ,  I-hun Song ,  Chang-jung Kim ,  Sang-hun Jeon

IPC: H01J27/00 ,  H04N9/04 ,  H04N5/3745 ,  H01L27/146

CPC classification number: H04N9/045 ,  H01L27/14643 ,  H04N5/3745

Abstract: Image sensors and methods of operating the same. An image sensor includes a pixel array including a plurality of pixels. Each of the plurality of pixels includes a photo sensor, the voltage-current characteristics of which vary according to energy of incident light, and that generates a sense current determined by the energy of the incident light; a reset unit that is activated to generate a reference current, according to a reset signal for resetting at least one of the plurality of pixels; and a conversion unit that converts the sense current and the reference current into a sense voltage and a reference voltage, respectively.

Abstract translation: 图像传感器及其操作方法。 图像传感器包括包括多个像素的像素阵列。 多个像素中的每一个包括光电传感器，其电压 - 电流特性根据入射光的能量而变化，并且产生由入射光的能量确定的感测电流; 根据用于复位所述多个像素中的至少一个的复位信号，被激活以产生参考电流的复位单元; 以及转换单元，其将感测电流和参考电流分别转换为感测电压和参考电压。

公开(公告)号：US08638163B2

公开(公告)日：2014-01-28

申请号：US13550848

申请日：2012-07-17

Applicant: Ho-jung Kim ,  U-in Chung ,  Jai-kwang Shin

Inventor： Ho-jung Kim ,  U-in Chung ,  Jai-kwang Shin

IPC: G05F1/10

CPC classification number: H01L29/78684 ,  G11C29/12005

Abstract: A semiconductor device and a method of operating the semiconductor device. The semiconductor device includes a voltage generator configured to generate a test voltage, a graphene transistor configured to receive a gate-source voltage based on the test voltage, and a detector configured to detect whether the gate-source voltage is a Dirac voltage of the graphene transistor, and output a feedback signal applied to the voltage generator indicating whether the gate-source voltage is the Dirac voltage.

Abstract translation: 一种半导体器件和操作半导体器件的方法。 半导体器件包括被配置为产生测试电压的电压发生器，被配置为基于测试电压接收栅极 - 源极电压的石墨烯晶体管，以及检测器，被配置为检测栅极 - 源极电压是否为石墨烯的狄拉克电压 并输出施加到电压发生器的反馈信号，指示栅极 - 源极电压是否为狄拉克电压。

公开(公告)号：US20130069714A1

公开(公告)日：2013-03-21

申请号：US13550848

申请日：2012-07-17

Applicant: Ho-jung Kim ,  U-in Chung ,  Jai-kwang Shin

Inventor： Ho-jung Kim ,  U-in Chung ,  Jai-kwang Shin

IPC: G05F1/10

CPC classification number: H01L29/78684 ,  G11C29/12005

Abstract: A semiconductor device and a method of operating the semiconductor device. The semiconductor device includes a voltage generator configured to generate a test voltage, a graphene transistor configured to receive a gate-source voltage based on the test voltage, and a detector configured to detect whether the gate-source voltage is a Dirac voltage of the graphene transistor, and output a feedback signal applied to the voltage generator indicating whether the gate-source voltage is the Dirac voltage.

Abstract translation: 一种半导体器件和操作半导体器件的方法。 半导体器件包括被配置为产生测试电压的电压发生器，被配置为基于测试电压接收栅极 - 源极电压的石墨烯晶体管，以及检测器，被配置为检测栅极 - 源极电压是否为石墨烯的狄拉克电压 并输出施加到电压发生器的反馈信号，指示栅极 - 源极电压是否为狄拉克电压。

公开(公告)号：US20050145932A1

公开(公告)日：2005-07-07

申请号：US10780067

申请日：2004-02-17

Applicant: Tai-su Park ,  Eui-Joon Yoon ,  U-In Chung ,  Si-Young Choi ,  Jong-Ho Lee

Inventor： Tai-su Park ,  Eui-Joon Yoon ,  U-In Chung ,  Si-Young Choi ,  Jong-Ho Lee

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/786 ,  H01L29/10

CPC classification number: H01L29/7851 ,  H01L29/66795 ,  H01L29/7854

Abstract: A field effect transistor can include a vertical channel protruding from a substrate including a source/drain region junction between the vertical channel and the substrate, and an insulating layer extending on a side wall of the vertical channel toward the substrate to beyond the source/drain region junction. The transistor can also include a nitride layer extending on the side wall away from the substrate to beyond the insulating layer, a second insulating layer extending on the side wall that is separated from the channel by the nitride layer, and a gate electrode extending on the side wall toward the substrate to beyond the source/drain region junction. Related methods are also disclosed.

Abstract translation: 场效应晶体管可以包括从包括垂直沟道和衬底之间的源极/漏极区域的衬底突出的垂直沟道，以及在垂直沟道的侧壁上朝衬底延伸超过源/漏极的绝缘层 区域交界处 晶体管还可以包括在离开衬底的侧壁上延伸超过绝缘层的氮化物层，在侧壁上延伸的第二绝缘层，其通过氮化物层与沟道分离，以及栅电极 侧壁朝向衬底以超出源/漏区结。 还公开了相关方法。

公开(公告)号：US5560778A

公开(公告)日：1996-10-01

申请号：US465015

申请日：1995-06-05

Applicant: In-Seon Park ,  Myoung-Bum Lee ,  Chang-Gee Hong ,  Chang-Gyu Kim ,  U-In Chung

Inventor： In-Seon Park ,  Myoung-Bum Lee ,  Chang-Gee Hong ,  Chang-Gyu Kim ,  U-In Chung

IPC: H01L21/205 ,  C23C16/02 ,  C23C16/40 ,  C23C16/44 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/3205 ,  C23C16/00

CPC classification number: H01L21/02164 ,  C23C16/0245 ,  C23C16/402 ,  C23C16/44 ,  H01L21/02271 ,  H01L21/02315 ,  H01L21/31051 ,  H01L21/31608

Abstract: A deposition rate of a dielectric material is varied with the electrical polarity of an underlying layer to obtain excellent deposition and planarization characteristics. A conductive layer and the underlying dielectric are surface-treated to have different electrical polarities so that the dielectric is formed by using the difference of deposition rates of the dielectric material between that on the conductive layer and that on the underlying dielectric. A CVD apparatus having a DC power source connected between a susceptor and a gas injection portion thereof is provided. The deposition and planarization can be performed at low temperatures and are simplified in process.

Abstract translation: 介电材料的沉积速率随着下层的电极性而变化，以获得优异的沉积和平坦化特性。 导电层和下面的电介质被表面处理以具有不同的电极性，使得通过使用电介质材料在导电层上和在下面的电介质之间的沉积速率的差异来形成电介质。 提供了一种具有连接在基座和其气体注入部分之间的直流电源的CVD装置。 沉积和平坦化可以在低温下进行并且在工艺上被简化。