公开(公告)号：US07727870B2

公开(公告)日：2010-06-01

申请号：US11737496

申请日：2007-04-19

申请人： Da Zhang ,  Xiangzheng Bo ,  Venkat R. Kolagunta

发明人： Da Zhang ,  Xiangzheng Bo ,  Venkat R. Kolagunta

IPC分类号： H01L21/3205

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： A method for forming a semiconductor device includes providing a substrate and forming a p-channel device and an n-channel device, each of the p-channel device and the n-channel device comprising a source, a drain, and a gate, the p-channel device having a first sidewall spacer and the n-channel device having a second sidewall spacer. The method further includes forming a liner and forming a tensile stressor layer over the liner and removing a portion of the tensile stressor layer from a region overlying the p-channel device. The method further includes transferring a stress characteristic of an overlying portion of a remaining portion of the tensile stressor layer to a channel of the n-channel device. The method further includes using the remaining portion of the tensile stressor layer as a hard mask, forming a first recess and a second recess adjacent the gate of the p-channel device.

摘要翻译： 一种用于形成半导体器件的方法包括提供衬底并形成p沟道器件和n沟道器件，每个p沟道器件和n沟道器件包括源极，漏极和栅极， p沟道器件具有第一侧壁间隔物，并且所述n沟道器件具有第二侧壁间隔物。 该方法还包括形成衬套并在衬套上形成拉伸应力层，并从覆盖p沟道器件的区域去除拉伸应力层的一部分。 该方法还包括将拉伸应力层的剩余部分的上覆部分的应力特性转移到n沟道器件的通道。 该方法还包括使用拉伸应力层的剩余部分作为硬掩模，形成邻近p沟道器件的栅极的第一凹槽和第二凹槽。

公开(公告)号：US07534674B2

公开(公告)日：2009-05-19

申请号：US11737492

申请日：2007-04-19

申请人： Sinan Goktepeli ,  Venkat R. Kolagunta

发明人： Sinan Goktepeli ,  Venkat R. Kolagunta

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L29/7843 ,  H01L21/31155 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/84 ,  H01L29/665 ,  H01L29/6653

摘要： First and second transistors are formed adjacent to each other. Both transistors have gate sidewall spacers removed. A stressor layer is formed overlying the first and second transistors. Stress in the stressor layer that overlies the first transistor is modified. Stress in the stressor layer that overlies the second transistor is permanently transferred to a channel of the second transistor. The stressor layer is removed except adjacent the gate electrode sidewalls of the first transistor and the second transistor where the stressor layer is used as gate sidewall spacers. Electrical contact to electrodes of the first transistor and the second transistor is made while using the gate sidewall spacers for determining a physical boundary of current electrodes of the first and second transistors. Subsequently formed first and a second stressors are positioned close to transistor channels of the first and second transistors.

摘要翻译： 第一和第二晶体管彼此相邻地形成。 两个晶体管都有去除栅侧壁间隔。 形成覆盖第一和第二晶体管的应力层。 改变了位于第一晶体管上的应力层的应力。 覆盖在第二晶体管上的应力层的应力永久地转移到第二晶体管的沟道。 去除应力源层，除了邻近第一晶体管的栅电极侧壁和应力层用作栅极侧壁间隔物的第二晶体管。 在使用用于确定第一和第二晶体管的电流电极的物理边界的栅极侧壁间隔物的同时，进行与第一晶体管和第二晶体管的电极的电接触。 随后形成第一和第二应力源靠近第一和第二晶体管的晶体管通道。

公开(公告)号：US07479465B2

公开(公告)日：2009-01-20

申请号：US11460748

申请日：2006-07-28

申请人： Gregory S. Spencer ,  Venkat R. Kolagunta ,  Narayanan C. Ramani ,  Vishal P. Trivedi

发明人： Gregory S. Spencer ,  Venkat R. Kolagunta ,  Narayanan C. Ramani ,  Vishal P. Trivedi

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L29/7833 ,  H01L21/26506 ,  H01L21/268 ,  H01L21/3105 ,  H01L29/6653 ,  H01L29/7843

摘要： A strained semiconductor layer is achieved by a method for transferring stress from a dielectric layer to a semiconductor layer. The method comprises providing a substrate having a semiconductor layer. A dielectric layer having a stress is formed over the semiconductor layer. A radiation anneal is applied over the dielectric layer of a duration not exceeding 10 milliseconds to cause the stress of the dielectric layer to create a stress in the semiconductor layer. The dielectric layer may then be removed. At least a portion of the stress in the semiconductor layer remains in the semiconductor layer after the dielectric layer is removed. The radiation anneal can be either by using either a laser beam or a flash tool. The radiation anneal can also be used to activate source/drain regions.

摘要翻译： 通过用于将应力从电介质层传递到半导体层的方法来实现应变半导体层。 该方法包括提供具有半导体层的衬底。 在半导体层上形成具有应力的电介质层。 在电介质层上施加辐射退火，持续时间不超过10毫秒，导致电介质层的应力在半导体层中产生应力。 然后可以去除电介质层。 在除去介电层之后，半导体层中至少一部分应力保留在半导体层中。 辐射退火可以通过使用激光束或闪光工具。 辐射退火也可用于激活源极/漏极区域。

公开(公告)号：US07420202B2

公开(公告)日：2008-09-02

申请号：US11269303

申请日：2005-11-08

申请人： Vance H. Adams ,  Paul A. Grudowski ,  Venkat R. Kolagunta ,  Brian A. Winstead

发明人： Vance H. Adams ,  Paul A. Grudowski ,  Venkat R. Kolagunta ,  Brian A. Winstead

IPC分类号： H01L29/06 ,  H01L21/31

CPC分类号： H01L21/84 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/7843

摘要： An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure.

摘要翻译： 电子器件可以包括第一导电类型的晶体管结构，场隔离区域和覆盖场隔离区域的第一应力类型的层。 例如，晶体管结构可以是p沟道晶体管结构，并且第一应力类型可以是拉伸的，或者晶体管结构可以是n沟道晶体管结构，并且第一应力类型可以是压缩的。 晶体管结构可以包括位于有源区内的沟道区。 有源区域的边缘包括沟道区域和场隔离区域之间的界面。 从顶视图，该层可以包括位于活动区域边缘附近的边缘。 边缘之间的位置关系可以影响晶体管结构的沟道区内的载流子迁移率。

公开(公告)号：US20080173957A1

公开(公告)日：2008-07-24

申请号：US11848612

申请日：2007-08-31

申请人： Leo Mathew ,  Venkat R. Kolagunta ,  David C. Sing

发明人： Leo Mathew ,  Venkat R. Kolagunta ,  David C. Sing

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/26506 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/785 ,  H01L29/78624 ,  H01L2924/0002 ,  Y10S438/981 ,  H01L2924/00

摘要： A method for forming a semiconductor device including forming a semiconductor substrate; forming a gate electrode over the semiconductor substrate having a first side and a second side, and forming a gate dielectric under the gate electrode. The gate dielectric has a first area under the gate electrode and adjacent the first side of the gate electrode, a second area under the gate electrode and adjacent the second side of the gate electrode, and a third area under the gate electrode that is between the first area and the second area, wherein the first area is thinner than the second area, and the third area is thinner than the first area and is thinner than the second area.

摘要翻译： 一种形成半导体器件的方法，包括形成半导体衬底; 在具有第一侧和第二侧的半导体衬底上形成栅电极，以及在栅极下形成栅极电介质。 栅极电介质具有栅电极下方的第一区域，并且与栅电极的第一侧相邻，第二区域在栅电极下方并且邻近栅电极的第二侧，栅极下方的第三区域位于栅电极之间 第一区域和第二区域，其中第一区域比第二区域薄，第三区域比第一区域薄，并且比第二区域薄。

公开(公告)号：US20080026599A1

公开(公告)日：2008-01-31

申请号：US11460748

申请日：2006-07-28

申请人： Gregory S. Spencer ,  Venkat R. Kolagunta ,  Narayanan C. Ramani ,  Vishal P. Trivedi

发明人： Gregory S. Spencer ,  Venkat R. Kolagunta ,  Narayanan C. Ramani ,  Vishal P. Trivedi

IPC分类号： H01L21/00

CPC分类号： H01L29/7833 ,  H01L21/26506 ,  H01L21/268 ,  H01L21/3105 ,  H01L29/6653 ,  H01L29/7843

摘要： A strained semiconductor layer is achieved by a method for transferring stress from a dielectric layer to a semiconductor layer. The method comprises providing a substrate having a semiconductor layer. A dielectric layer having a stress is formed over the semiconductor layer. A radiation anneal is applied over the dielectric layer of a duration not exceeding 10 milliseconds to cause the stress of the dielectric layer to create a stress in the semiconductor layer. The dielectric layer may then be removed. At least a portion of the stress in the semiconductor layer remains in the semiconductor layer after the dielectric layer is removed. The radiation anneal can be either by using either a laser beam or a flash tool. The radiation anneal can also be used to activate source/drain regions.

摘要翻译： 通过用于将应力从电介质层传递到半导体层的方法来实现应变半导体层。 该方法包括提供具有半导体层的衬底。 在半导体层上形成具有应力的电介质层。 在电介质层上施加辐射退火，持续时间不超过10毫秒，导致电介质层的应力在半导体层中产生应力。 然后可以去除电介质层。 在除去介电层之后，半导体层中至少一部分应力保留在半导体层中。 辐射退火可以通过使用激光束或闪光工具。 辐射退火也可用于激活源极/漏极区域。

公开(公告)号：US07161199B2

公开(公告)日：2007-01-09

申请号：US10925084

申请日：2004-08-24

申请人： Jian Chen ,  Michael A. Mendicino ,  Vance H. Adams ,  Choh-Fei Yeap ,  Venkat R. Kolagunta

发明人： Jian Chen ,  Michael A. Mendicino ,  Vance H. Adams ,  Choh-Fei Yeap ,  Venkat R. Kolagunta

IPC分类号： H01L29/76

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828

摘要： A transistor comprises a source and drain positioned within an active region. A gate overlies a channel area of the active region, wherein the channel region separates the source and drain. The transistor further comprises at least one stress modifier and capacitive reduction feature extending from the source to the drain and underlying the gate for reducing capacitance associated with the gate, source and drain. The at least one stress modifier and capacitive reduction feature comprises dielectric and includes a shape defined at least partially by the active region.

摘要翻译： 晶体管包括位于有源区域内的源极和漏极。 栅极覆盖有源区的沟道区，其中沟道区分离源极和漏极。 晶体管还包括至少一个应力调节器和电容降低特征，其从源极延伸到漏极并且在栅极下方，用于减小与栅极，源极和漏极相关联的电容。 所述至少一个应力调节剂和电容还原特征包括电介质并且包括至少部分地由有源区限定的形状。

公开(公告)号：US07067868B2

公开(公告)日：2006-06-27

申请号：US10952676

申请日：2004-09-29

申请人： Voon-Yew Thean ,  Mariam G. Sadaka ,  Ted R. White ,  Alexander L. Barr ,  Venkat R. Kolagunta ,  Bich-Yen Nguyen ,  Victor H. Vartanian ,  Da Zhang

发明人： Voon-Yew Thean ,  Mariam G. Sadaka ,  Ted R. White ,  Alexander L. Barr ,  Venkat R. Kolagunta ,  Bich-Yen Nguyen ,  Victor H. Vartanian ,  Da Zhang

IPC分类号： H01L27/108

CPC分类号： H01L29/785 ,  H01L29/42392 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/7842 ,  H01L29/78621 ,  H01L29/78648 ,  H01L29/78687

摘要： A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.

公开(公告)号：US07018901B1

公开(公告)日：2006-03-28

申请号：US10954121

申请日：2004-09-29

申请人： Voon-Yew Thean ,  Mariam G. Sadaka ,  Ted R. White ,  Alexander L. Barr ,  Venkat R. Kolagunta ,  Bich-Yen Nguyen ,  Victor H. Vartanian ,  Da Zhang

发明人： Voon-Yew Thean ,  Mariam G. Sadaka ,  Ted R. White ,  Alexander L. Barr ,  Venkat R. Kolagunta ,  Bich-Yen Nguyen ,  Victor H. Vartanian ,  Da Zhang

IPC分类号： H01L21/336

CPC分类号： H01L21/2254 ,  H01L29/665 ,  H01L29/66787 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78648

摘要： A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.

摘要翻译： 半导体器件（10）通过将覆盖在优选硅的半导体层（16）上的栅极（22）定位而形成。 例如仅SiGe或Ge的半导体材料（26）形成在半导体层上方的栅极和源极/漏极区域附近。 热处理将应力源材料扩散到半导体层。 发生横向扩散以形成应变通道（17），其中应力材料层（30）紧邻应变通道。 延伸植入物从应力源材料层的第一部分产生源和漏植入物。 应力源材料层的第二部分保留在应变通道和源极和漏极植入物之间的通道中。 因此，在应变通道中形成异质结。 在另一种形式中，发生应力源材料的氧化而不是延伸植入物以形成应变通道。