公开(公告)号：US07416945B1

公开(公告)日：2008-08-26

申请号：US11676403

申请日：2007-02-19

Applicant: Ramachandran Muralidhar ,  Rajesh A. Rao ,  Matthew T. Herrick ,  Narayanan C. Ramani ,  Robert F. Steimle

Inventor： Ramachandran Muralidhar ,  Rajesh A. Rao ,  Matthew T. Herrick ,  Narayanan C. Ramani ,  Robert F. Steimle

IPC: H01L21/336

CPC classification number: H01L21/28273 ,  B82Y10/00 ,  H01L27/115 ,  H01L27/11521

Abstract: A method forms a split gate memory device. A layer of select gate material over a substrate is patterned to form a first sidewall. A sacrificial spacer is formed adjacent to the first sidewall. Nanoclusters are formed over the substrate including on the sacrificial spacer. The sacrificial spacer is removed after the forming the layer of nanoclusters, wherein nanoclusters formed on the sacrificial spacer are removed and other nanoclusters remain. A layer of control gate material is formed over the substrate after the sacrificial spacer is removed. A control gate of a split gate memory device is formed from the layer of control gate material, wherein the control gate is located over remaining nanoclusters.

Abstract translation: 一种方法形成分离栅极存储器件。 将衬底上的选择栅极材料层图案化以形成第一侧壁。 邻近第一侧壁形成牺牲隔离物。 纳米团簇形成在包括在牺牲间隔物上的衬底上。 在形成纳米团簇层之后去除牺牲隔离物，其中除去在牺牲隔离物上形成的纳米团簇并保留其他纳米团簇。 在除去牺牲间隔物之后，在衬底上形成一层控制栅极材料。 分离栅极存储器件的控制栅极由控制栅极材料层形成，其中控制栅极位于剩余的纳米簇上。

公开(公告)号：US08659087B2

公开(公告)日：2014-02-25

申请号：US12639394

申请日：2009-12-16

Applicant: Olubunmi O. Adetutu ,  Tien Ying Luo ,  Narayanan C. Ramani

Inventor： Olubunmi O. Adetutu ,  Tien Ying Luo ,  Narayanan C. Ramani

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/82345 ,  H01L21/823842 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7833

Abstract: A transistor structure of an electronic device can include a gate dielectric layer and a gate electrode. The gate electrode can have a surface portion between the gate dielectric layer and the rest of the gate electrode. The surface portion can be formed such that another portion of the gate electrode primarily sets the effective work function in the finished transistor structure.

Abstract translation: 电子器件的晶体管结构可以包括栅极介电层和栅电极。 栅极电极可以在栅极电介质层和栅电极的其余部分之间具有表面部分。 表面部分可以形成为使得栅电极的另一部分主要在最终晶体管结构中设置有效功函数。

公开(公告)号：US20100090287A1

公开(公告)日：2010-04-15

申请号：US12639394

申请日：2009-12-16

Applicant: Olubunmi O. Adetutu ,  Tien Ying Luo ,  Narayanan C. Ramani

Inventor： Olubunmi O. Adetutu ,  Tien Ying Luo ,  Narayanan C. Ramani

IPC: H01L27/088 ,  H01L29/51

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/82345 ,  H01L21/823842 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7833

Abstract: A transistor structure of an electronic device can include a gate dielectric layer and a gate electrode. The gate electrode can have a surface portion between the gate dielectric layer and the rest of the gate electrode. The surface portion can be formed such that another portion of the gate electrode primarily sets the effective work function in the finished transistor structure.

Abstract translation: 电子器件的晶体管结构可以包括栅极介电层和栅电极。 栅极电极可以在栅极电介质层和栅电极的其余部分之间具有表面部分。 表面部分可以形成为使得栅电极的另一部分主要在最终晶体管结构中设置有效功函数。

公开(公告)号：US07514313B2

公开(公告)日：2009-04-07

申请号：US11400945

申请日：2006-04-10

Applicant: Omar Zia ,  Da Zhang ,  Venkat R. Kolagunta ,  Narayanan C. Ramani ,  Bich-Yen Nguyen

Inventor： Omar Zia ,  Da Zhang ,  Venkat R. Kolagunta ,  Narayanan C. Ramani ,  Bich-Yen Nguyen

IPC: H01L21/98 ,  H01L21/8238

CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

Abstract: A process of forming an electronic device can include forming an insulating layer over first and second active regions, and a field isolation region. The process can also include forming a seed layer and exposing the first active region. The process can further include selectively forming a first and second semiconductor layer over the first active region and the seed layer, respectively. The first and second semiconductor layers can be spaced-apart from each other. In one aspect, the process can include selectively forming the first and second semiconductor layers simultaneously at a substantially same point in time. In another aspect, an electronic device can include first and second transistor structures separated by a field isolation region and electrically connected by a conductive member. A semiconductor island, designed to be electrically floating, can lie between the conductive member and the base layer.

Abstract translation: 形成电子器件的工艺可以包括在第一和第二有源区上形成绝缘层和场隔离区。 该方法还可以包括形成种子层并暴露第一有源区。 该方法还可以包括分别在第一有源区和种子层上选择性地形成第一和第二半导体层。 第一和第二半导体层可以彼此间隔开。 在一个方面，该方法可以包括在基本相同的时间点同时选择性地形成第一和第二半导体层。 在另一方面，电子设备可以包括由场隔离区分隔开并由导电构件电连接的第一和第二晶体管结构。 设计为电浮置的半导体岛可以位于导电构件和基底层之间。

公开(公告)号：US07651935B2

公开(公告)日：2010-01-26

申请号：US11237346

申请日：2005-09-27

Applicant: Olubunmi O. Adetutu ,  Tien Ying Luo ,  Narayanan C. Ramani

Inventor： Olubunmi O. Adetutu ,  Tien Ying Luo ,  Narayanan C. Ramani

IPC: H01L21/3205

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/82345 ,  H01L21/823842 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7833

Abstract: A transistor structure of an electronic device can include a gate dielectric layer and a gate electrode. The gate electrode can have a surface portion between the gate dielectric layer and the rest of the gate electrode. The surface portion can be formed such that another portion of the gate electrode primarily sets the effective work function in the finished transistor structure.

Abstract translation: 电子器件的晶体管结构可以包括栅极介电层和栅电极。 栅极电极可以在栅极电介质层和栅电极的其余部分之间具有表面部分。 表面部分可以形成为使得栅电极的另一部分主要在最终晶体管结构中设置有效功函数。

公开(公告)号：US07479465B2

公开(公告)日：2009-01-20

申请号：US11460748

申请日：2006-07-28

Applicant: Gregory S. Spencer ,  Venkat R. Kolagunta ,  Narayanan C. Ramani ,  Vishal P. Trivedi

Inventor： Gregory S. Spencer ,  Venkat R. Kolagunta ,  Narayanan C. Ramani ,  Vishal P. Trivedi

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L29/7833 ,  H01L21/26506 ,  H01L21/268 ,  H01L21/3105 ,  H01L29/6653 ,  H01L29/7843

Abstract: A strained semiconductor layer is achieved by a method for transferring stress from a dielectric layer to a semiconductor layer. The method comprises providing a substrate having a semiconductor layer. A dielectric layer having a stress is formed over the semiconductor layer. A radiation anneal is applied over the dielectric layer of a duration not exceeding 10 milliseconds to cause the stress of the dielectric layer to create a stress in the semiconductor layer. The dielectric layer may then be removed. At least a portion of the stress in the semiconductor layer remains in the semiconductor layer after the dielectric layer is removed. The radiation anneal can be either by using either a laser beam or a flash tool. The radiation anneal can also be used to activate source/drain regions.

Abstract translation: 通过用于将应力从电介质层传递到半导体层的方法来实现应变半导体层。 该方法包括提供具有半导体层的衬底。 在半导体层上形成具有应力的电介质层。 在电介质层上施加辐射退火，持续时间不超过10毫秒，导致电介质层的应力在半导体层中产生应力。 然后可以去除电介质层。 在除去介电层之后，半导体层中至少一部分应力保留在半导体层中。 辐射退火可以通过使用激光束或闪光工具。 辐射退火也可用于激活源极/漏极区域。

公开(公告)号：US20080199996A1

公开(公告)日：2008-08-21

申请号：US11676403

申请日：2007-02-19

Applicant: Ramachandran Muralidhar ,  Rajesh A. Rao ,  Matthew T. Herrick ,  Narayanan C. Ramani ,  Robert F. Steimle

Inventor： Ramachandran Muralidhar ,  Rajesh A. Rao ,  Matthew T. Herrick ,  Narayanan C. Ramani ,  Robert F. Steimle

IPC: H01L21/336

CPC classification number: H01L21/28273 ,  B82Y10/00 ,  H01L27/115 ,  H01L27/11521

Abstract: A method forms a split gate memory device. A layer of select gate material over a substrate is patterned to form a first sidewall. A sacrificial spacer is formed adjacent to the first sidewall. Nanoclusters are formed over the substrate including on the sacrificial spacer. The sacrificial spacer is removed after the forming the layer of nanoclusters, wherein nanoclusters formed on the sacrificial spacer are removed and other nanoclusters remain. A layer of control gate material is formed over the substrate after the sacrificial spacer is removed. A control gate of a split gate memory device is formed from the layer of control gate material, wherein the control gate is located over remaining nanoclusters.

Abstract translation: 一种方法形成分离栅极存储器件。 将衬底上的选择栅极材料层图案化以形成第一侧壁。 邻近第一侧壁形成牺牲隔离物。 纳米团簇形成在包括在牺牲间隔物上的衬底上。 在形成纳米团簇层之后去除牺牲隔离物，其中在牺牲隔离物上形成的纳米团簇被去除并且其它纳米团簇保留。 在除去牺牲间隔物之后，在衬底上形成一层控制栅极材料。 分离栅极存储器件的控制栅极由控制栅极材料层形成，其中控制栅极位于剩余的纳米簇上。

公开(公告)号：US20080026599A1

公开(公告)日：2008-01-31

申请号：US11460748

申请日：2006-07-28

Applicant: Gregory S. Spencer ,  Venkat R. Kolagunta ,  Narayanan C. Ramani ,  Vishal P. Trivedi

Inventor： Gregory S. Spencer ,  Venkat R. Kolagunta ,  Narayanan C. Ramani ,  Vishal P. Trivedi

IPC: H01L21/00

CPC classification number: H01L29/7833 ,  H01L21/26506 ,  H01L21/268 ,  H01L21/3105 ,  H01L29/6653 ,  H01L29/7843

Abstract: A strained semiconductor layer is achieved by a method for transferring stress from a dielectric layer to a semiconductor layer. The method comprises providing a substrate having a semiconductor layer. A dielectric layer having a stress is formed over the semiconductor layer. A radiation anneal is applied over the dielectric layer of a duration not exceeding 10 milliseconds to cause the stress of the dielectric layer to create a stress in the semiconductor layer. The dielectric layer may then be removed. At least a portion of the stress in the semiconductor layer remains in the semiconductor layer after the dielectric layer is removed. The radiation anneal can be either by using either a laser beam or a flash tool. The radiation anneal can also be used to activate source/drain regions.

Abstract translation: 通过用于将应力从电介质层传递到半导体层的方法来实现应变半导体层。 该方法包括提供具有半导体层的衬底。 在半导体层上形成具有应力的电介质层。 在电介质层上施加辐射退火，持续时间不超过10毫秒，导致电介质层的应力在半导体层中产生应力。 然后可以去除电介质层。 在除去介电层之后，半导体层中至少一部分应力保留在半导体层中。 辐射退火可以通过使用激光束或闪光工具。 辐射退火也可用于激活源极/漏极区域。