公开(公告)号：US07741658B2

公开(公告)日：2010-06-22

申请号：US11842437

申请日：2007-08-21

Applicant: Yaocheng Liu ,  Zhijiong Luo ,  Huilong Zhu

Inventor： Yaocheng Liu ,  Zhijiong Luo ,  Huilong Zhu

IPC: H01L31/0328

CPC classification number: H01L21/26506 ,  H01L21/268 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

Abstract: The embodiments of the invention comprise a self-aligned super stressed p-type field effect transistor (PFET). More specifically, a field effect transistor comprises a channel region comprising N-doped material and a gate above the channel region. The field effect transistor also includes a source region on a first side of the channel region and a drain region on a second side of the channel region opposite the first side. The source and drain regions each comprise silicon germanium, wherein the silicon germanium has structural indicia of epitaxial growth.

Abstract translation: 本发明的实施例包括自对准超应力p型场效应晶体管（PFET）。 更具体地，场效应晶体管包括包含N掺杂材料的沟道区和沟道区上方的栅。 场效应晶体管还包括在沟道区的第一侧上的源极区域和与第一侧相对的沟道区域的第二侧上的漏极区域。 源极和漏极区域各自包含硅锗，其中硅锗具有外延生长的结构标记。

公开(公告)号：US20090081836A1

公开(公告)日：2009-03-26

申请号：US11860127

申请日：2007-09-24

Applicant: Yaocheng Liu ,  Qiqing C. Ouyang ,  Kathryn T. Schonenberg ,  Chun-Yung Sung

Inventor： Yaocheng Liu ,  Qiqing C. Ouyang ,  Kathryn T. Schonenberg ,  Chun-Yung Sung

IPC: H01L21/265 ,  H01L21/8238

CPC classification number: H01L21/26506 ,  H01L21/268 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7848

Abstract: A method of forming crystalline Si:C in source and drain regions is provided. After formation of shallow trench isolation and gate electrodes of field effect transistors, gate spacers are formed on gate electrodes. Preamorphization implantation is performed in the source and drain regions, followed by carbon implantation. The upper portion of the source and drain regions comprises an amorphous mixture of silicon, germanium, and/or carbon. An anti-reflective layer is deposited to enhance the absorption of a laser beam into the silicon substrate. The laser beam is scanned over the silicon substrate including the upper source and drain region with the amorphous mixture. The energy of the laser beam is controlled so that the temperature of the semiconductor substrate is above the melting temperature of the amorphous mixture but below the glass transition temperature of silicon oxide so that structural integrity of the semiconductor structure is preserved.

Abstract translation: 提供了在源极和漏极区域中形成晶体Si：C的方法。 在形成浅沟槽隔离和场效应晶体管的栅电极之后，在栅电极上形成栅极间隔物。 在源极和漏极区域中进行前置放电，随后进行碳注入。 源区和漏区的上部包括硅，锗和/或碳的无定形混合物。 沉积抗反射层以增强激光束到硅衬底中的吸收。 激光束在包括具有无定形混合物的上源极和漏极区域的硅衬底上扫描。 控制激光束的能量使得半导体衬底的温度高于无定形混合物的熔融温度但低于氧化硅的玻璃化转变温度，从而保持了半导体结构的结构完整性。

公开(公告)号：US07485519B2

公开(公告)日：2009-02-03

申请号：US11693786

申请日：2007-03-30

Applicant: Dureseti Chidambarrao ,  William K. Henson ,  Yaocheng Liu

Inventor： Dureseti Chidambarrao ,  William K. Henson ,  Yaocheng Liu

IPC: H01L21/8238

CPC classification number: H01L29/66628 ,  H01L21/84 ,  H01L29/1083 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/78654

Abstract: A field effect transistor (“FET”) is formed to include a stress in a channel region of an active semiconductor region of an SOI substrate. A gate is formed to overlie the active semiconductor region, after which a sacrificial stressed layer is formed which overlies the gate and the active semiconductor region. Then, the SOI substrate is heated to cause a flowable dielectric material in a buried dielectric layer of the SOI substrate to soften and reflow. As a result of the reflowing, the sacrificial stressed layer induces stress in a channel region of the active semiconductor region underlying the gate. A source region and a drain region are formed in the active semiconductor region, desirably after removing the sacrificial stressed layer.

Abstract translation: 形成场效应晶体管（“FET”）以在SOI衬底的有源半导体区域的沟道区域中包括应力。 形成栅极覆盖有源半导体区域，之后形成覆盖在栅极和有源半导体区域上的牺牲应力层。 然后，加热SOI衬底，使SOI衬底的埋入介质层中的可流动介电材料软化和回流。 作为回流的结果，牺牲应力层在栅极下方的有源半导体区域的沟道区域中引起应力。 源极区域和漏极区域形成在有源半导体区域中，理想地在除去牺牲应力层之后。

公开(公告)号：US07473608B2

公开(公告)日：2009-01-06

申请号：US11840795

申请日：2007-08-17

Applicant: Jinghong H. Li ,  Yaocheng Liu ,  Zhijiong Luo ,  Anita Madan ,  Nivo Rovedo

Inventor： Jinghong H. Li ,  Yaocheng Liu ,  Zhijiong Luo ,  Anita Madan ,  Nivo Rovedo

IPC: H01L21/22

CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848 ,  Y10S257/90

Abstract: The present invention relates to a semiconductor device comprising at least one n-channel field effect transistor (n-FET). Specifically, the n-FET comprises first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single crystal semiconductor. The first patterned stressor layer has a first carbon concentration and is located in source and drain (S/D) extension regions of the n-FET at a first depth. The second patterned stressor layer has a second, higher carbon concentration and is located in S/D regions of the n-FET at a second, deeper depth. Such an n-FET with the first and second patterned stressor layers of different carbon concentration and different depths provide improved stress profile for enhancing electron mobility in the channel region of the n-FET.

Abstract translation: 本发明涉及包括至少一个n沟道场效应晶体管（n-FET）的半导体器件。 具体地说，n-FET包括第一和第二图案应力层，它们都包含碳取代和拉伸应力单晶半导体。 第一图案应力层具有第一碳浓度并且位于第一深度处的n-FET的源极和漏极（S / D）延伸区域中。 第二图案应力层具有第二较高的碳浓度，并且位于第二较深深度处的n-FET的S / D区中。 这种具有不同碳浓度和不同深度的第一和第二图案应力层的n-FET提供了改善的应力分布，用于增强n-FET的沟道区域中的电子迁移率。

公开(公告)号：US20080258234A1

公开(公告)日：2008-10-23

申请号：US11738666

申请日：2007-04-23

Applicant: William K. Henson ,  Paul Chung-Muh Chang ,  Dureseti Chidambarrao ,  Ricardo A. Donaton ,  Yaocheng Liu ,  Shreesh Narasimha ,  Amanda L. Tessier

Inventor： William K. Henson ,  Paul Chung-Muh Chang ,  Dureseti Chidambarrao ,  Ricardo A. Donaton ,  Yaocheng Liu ,  Shreesh Narasimha ,  Amanda L. Tessier

IPC: H01L21/285 ,  H01L21/336

CPC classification number: H01L21/823807 ,  H01L21/28097 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76844 ,  H01L21/823864 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7843

Abstract: A semiconductor structure provides lower parasitic capacitance between the gate electrode and contact vias while providing substantially the same level of stress applied by a nitride liner as conventional MOSFETs by reducing the height of the gate electrode and maintaining substantially the same height for the gate spacer. The nitride liner contacts only the outer sidewalls of the gate spacer, while not contacting inner sidewalls, or only a small area of the inner sidewalls of the gate spacer, therefore applying substantially the same level of stress to the channel of the MOSFET as conventional MOSFETs. The volume surrounded by the gate spacer and located above the gate electrode is either filled with a low-k dielectric material or occupied by a cavity having a dielectric constant of substantially 1.0. The reduced height of the gate electrode and the low-k dielectric gate filler or the cavity reduces the parasitic capacitance.

Abstract translation: 半导体结构在栅电极和接触通孔之间提供较低的寄生电容，同时通过降低栅极电极的高度并保持与栅极间隔件基本上相同的高度，提供与常规MOSFET相同的氮化物衬垫施加的基本相同的应力水平。 氮化物衬垫仅接触栅极间隔物的外侧壁，而不接触内侧壁，或者仅接触栅极隔离物的内侧壁的小面积，因此与常规MOSFET相比施加与MOSFET的通道基本相同的应力水平 。 由栅极间隔物围绕并位于栅极电极上方的体积填充有低k电介质材料或由具有基本上1.0的介电常数的空腔占据。 栅电极和低k电介质栅极填充物或空腔的降低的高度减小了寄生电容。

公开(公告)号：US20080217697A1

公开(公告)日：2008-09-11

申请号：US12127171

申请日：2008-05-27

Applicant: Yaocheng Liu ,  Alexander Reznicek ,  Devendra K. Sadana

Inventor： Yaocheng Liu ,  Alexander Reznicek ,  Devendra K. Sadana

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/823842 ,  H01L21/28035 ,  H01L21/32155 ,  H01L29/4916

Abstract: A method to control the poly-Si depletion effect in CMOS structures utilizing a gas phase doping process which is capable of providing a high concentration of dopant atoms at the gate dielectric/poly-Si interface is provided. The present invention also provides CMOS structure including, for example, nFETs and/or pFETs, that are fabricated utilizing the gas phase doping technique described herein.

Abstract translation: 提供了一种利用气相掺杂工艺在CMOS结构中控制多晶硅耗尽效应的方法，该方法能够在栅极电介质/多晶硅界面处提供高浓度的掺杂剂原子。 本发明还提供了使用本文所述的气相掺杂技术制造的包括例如nFET和/或pFET的CMOS结构。

公开(公告)号：US20080191281A1

公开(公告)日：2008-08-14

申请号：US11673716

申请日：2007-02-12

Applicant: Dureseti Chidambarrao ,  William K. Henson ,  Yaocheng Liu

Inventor： Dureseti Chidambarrao ,  William K. Henson ,  Yaocheng Liu

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L29/78603 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7843

Abstract: A method is provided for fabricating a field effect transistor (“FET”) having a channel region in a semiconductor-on-insulator (“SOI”) layer of an SOI substrate. Desirably, in such method, a sacrificial stressed layer is formed to overlie a first portion of an active semiconductor region but not overlie second portion of the active semiconductor region which shares a common boundary with the first portion. After forming trenches in the SOI layer, the SOI substrate is heated with the stressed layer thereon sufficiently to cause the stressed layer to relax, thereby causing the stressed layer to apply a first stress to the first portion and to apply a second stress to the second portion. For example, when the first stress is tensile, the second stress is compressive, or the first stress can be compressive when the second stress is tensile. Desirably, the stressed layer is then removed to expose the first and second portions of the active semiconductor region. Desirably, the field effect transistor (“FET”) is formed to include (i) a source region in the first portion, (ii) a drain region in the first portion, and (iii) a channel region in the second portion.

Abstract translation: 提供一种用于制造在SOI衬底的绝缘体上半导体（“SOI”）层中具有沟道区的场效应晶体管（“FET”）的方法。 理想地，在这种方法中，牺牲应力层形成为覆盖有源半导体区域的第一部分，但不覆盖与第一部分共用公共边界的有源半导体区域的第二部分。 在SOI层中形成沟槽之后，将SOI衬底上的应力层充分加热，使得应力层松弛，从而使应力层对第一部分施加第一应力并向第二部分施加第二应力 一部分。 例如，当第一应力是拉伸时，第二应力是压缩的，或者当第二应力是拉伸时，第一应力可以是压缩的。 理想地，应力层被去除以暴露有源半导体区域的第一和第二部分。 期望地，场效应晶体管（“FET”）形成为包括（i）第一部分中的源极区域，（ii）第一部分中的漏极区域，以及（iii）第二部分中的沟道区域。

公开(公告)号：US20080191243A1

公开(公告)日：2008-08-14

申请号：US11672599

申请日：2007-02-08

Applicant: Yaocheng Liu ,  Shreesh Narasimha ,  Katsunori Onishi ,  Kern Rim

Inventor： Yaocheng Liu ,  Shreesh Narasimha ,  Katsunori Onishi ,  Kern Rim

IPC: H01L27/092 ,  H01L29/778 ,  H01L21/8238 ,  H01L21/336

CPC classification number: H01L27/1203 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/28247 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

Abstract: Disclosed are embodiments of an n-FET structure with silicon carbon S/D regions completely contained inside amorphization regions and with a carbon-free gate electrode. Containing carbon within the amorphization regions, ensures that all of the carbon is substitutional following re-crystallization to maximize the tensile stress imparted on channel region. The gate stack is capped during carbon implantation so the risk of carbon entering the gate stack and degrading the conductivity of the gate polysilicon and/or damaging the gate oxide is essentially eliminated. Thus, the carbon implant regions can be formed deeper. Deeper S/D carbon implants which are completely amorphized and then re-crystallized provide greater tensile stress on the n-FET channel region to further optimize electron mobility. Additionally, the gate electrode is uncapped during the n-type dopant process, so the n-type dopant dose in the gate electrode can be at least great as the dose in the S/D regions.

Abstract translation: 公开了具有完全包含在非晶化区域内和具有无碳栅电极的硅碳S / D区域的n-FET结构的实施方案。 在非晶化区域内含有碳，确保在再结晶后所有碳都是取代的，以最大限度地增加通道区域上施加的拉伸应力。 在碳注入期间，栅极堆叠被封盖，从而基本上消除了碳进入栅极堆叠并降低栅极多晶硅的导电性和/或损坏栅极氧化物的风险。 因此，可以更深地形成碳注入区域。 完全非晶化然后再结晶的深S / D碳植入物在n-FET沟道区域上提供更大的拉伸应力，以进一步优化电子迁移率。 此外，在n型掺杂剂处理期间，栅电极未被封装，因此栅电极中的n型掺杂剂剂量可以至少大于S / D区域中的剂量。

公开(公告)号：US20080090412A1

公开(公告)日：2008-04-17

申请号：US11548842

申请日：2006-10-12

Applicant: Thomas W. Dyer ,  Sunfei Fang ,  Jiang Yan ,  Jun Jung Kim ,  Yaocheng Liu ,  Huilong Zhu

Inventor： Thomas W. Dyer ,  Sunfei Fang ,  Jiang Yan ,  Jun Jung Kim ,  Yaocheng Liu ,  Huilong Zhu

IPC: H01L21/44

CPC classification number: H01L29/665 ,  H01L21/32 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659

Abstract: A method forms a gate conductor over a substrate, and simultaneously forms spacers on sides of the gate conductor and a gate cap on the top of the gate conductor. Isolation regions are formed in the substrate and the method implants an impurity into exposed regions of the substrate not protected by the gate conductor and the spacers to form source and drain regions. The method deposits a mask over the gate conductor, the spacers, and the source and drain regions. The mask is recessed to a level below a top of the gate conductor but above the source and drain regions, such that the spacers are exposed and the source and drain regions are protected by the mask. With the mask in place, the method then safely removes the spacers and the gate cap, without damaging the source/drain regions or the isolation regions (which are protected by the mask). Next, the method removes the mask and then forms silicide regions on the gate conductor and the source and drain regions.

Abstract translation: 一种方法在衬底上形成栅极导体，同时在栅极导体的侧面和栅极导体的顶部上形成栅极盖。 在衬底中形成隔离区域，并且该方法将杂质注入未被栅极导体和间隔物保护的衬底的暴露区域中以形成源区和漏区。 该方法在栅极导体，间隔物以及源极和漏极区域上沉积掩模。 掩模凹陷到栅极导体的顶部下方但在源极和漏极区域之上的水平面，使得间隔物被暴露，并且源极和漏极区域被掩模保护。 在掩模就位的情况下，该方法然后安全地去除间隔物和栅极盖，而不损坏源极/漏极区域或隔离区域（被掩模保护）。 接下来，该方法移除掩模，然后在栅极导体和源极和漏极区域上形成硅化物区域。

公开(公告)号：US20070281413A1

公开(公告)日：2007-12-06

申请号：US11840795

申请日：2007-08-17

Applicant: Jinghong Li ,  Yaocheng Liu ,  Zhijiong Luo ,  Anita Madan ,  Nivo Rovedo

Inventor： Jinghong Li ,  Yaocheng Liu ,  Zhijiong Luo ,  Anita Madan ,  Nivo Rovedo

IPC: H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848 ,  Y10S257/90

Abstract: The present invention relates to a semiconductor device comprising at least one n-channel field effect transistor (n-FET). Specifically, the n-FET comprises first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single crystal semiconductor. The first patterned stressor layer has a first carbon concentration and is located in source and drain (S/D) extension regions of the n-FET at a first depth. The second patterned stressor layer has a second, higher carbon concentration and is located in S/D regions of the n-FET at a second, deeper depth. Such an n-FET with the first and second patterned stressor layers of different carbon concentration and different depths provide improved stress profile for enhancing electron mobility in the channel region of the n-FET.

Abstract translation: 本发明涉及包括至少一个n沟道场效应晶体管（n-FET）的半导体器件。 具体地说，n-FET包括第一和第二图案应力层，它们都包含碳取代和拉伸应力单晶半导体。 第一图案应力层具有第一碳浓度并且位于第一深度处的n-FET的源极和漏极（S / D）延伸区域中。 第二图案应力层具有第二较高的碳浓度，并且位于第二较深深度处的n-FET的S / D区中。 这种具有不同碳浓度和不同深度的第一和第二图案应力层的n-FET提供了改善的应力分布，用于增强n-FET的沟道区域中的电子迁移率。