公开(公告)号：US11086628B2

公开(公告)日：2021-08-10

申请号：US15236882

申请日：2016-08-15

Applicant: Advanced Micro Devices, Inc.

Inventor： John M. King

IPC: G06F9/312 ,  G06F9/32 ,  G06F9/38 ,  G06F9/30 ,  G06F9/48

Abstract: A system and method for load queue (LDQ) and store queue (STQ) entry allocations at address generation time that maintains age-order of instructions is described. In particular, writing LDQ and STQ entries are delayed until address generation time. This allows the load and store operations to dispatch, and younger operations (which may not be store and load operations) to also dispatch and execute their instructions. The address generation of the load or store operation is held at an address generation scheduler queue (AGSQ) until a load or store queue entry is available for the operation. The tracking of load queue entries or store queue entries is effectively being done in the AGSQ instead of at the decode engine. The LDQ and STQ depth is not visible from a decode engine's perspective, and increases the effective processing and queue depth.

公开(公告)号：US10303480B2

公开(公告)日：2019-05-28

申请号：US14067564

申请日：2013-10-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： David A Kaplan ,  Daniel Hopper ,  John M. King ,  Jeff Rupley

IPC: G06F9/38 ,  G06F12/0875

Abstract: Embodiments herein provide for improved store-to-load-forwarding (STLF) logic and linear aliasing effect reduction logic. In one embodiment, a load instruction to be executed is selected. Whether a first linear address associated with said load instruction matches a linear address of a store instruction of a plurality of store instructions in a queue is determined. Data associated with said store instruction for executing said load instruction is forwarded, in response to determining that the first linear address matches the linear address of the store instruction.

公开(公告)号：US20180081810A1

公开(公告)日：2018-03-22

申请号：US15268798

申请日：2016-09-19

Applicant: Advanced Micro Devices, Inc.

Inventor： John M. King ,  Gregory W. Smaus

IPC: G06F12/0844 ,  G06F12/0877

CPC classification number: G06F12/0844 ,  G06F9/52 ,  G06F12/0815 ,  G06F12/0877 ,  G06F2212/1008 ,  G06F2212/1016 ,  G06F2212/1032

Abstract: The techniques described herein improve cache traffic performance in the context of contended lock instructions. More specifically, each core maintains a lock address contention table that stores addresses corresponding to contended lock instructions. The lock address contention table also includes a state value that indicates progress through a series of states meant to track whether a load by the core in a spin-loop associated with semaphore acquisition has obtained the semaphore in an exclusive state. Upon detecting that a load in a spin-loop has obtained the semaphore in an exclusive state, the core responds to incoming requests for access to the semaphore with negative acknowledgments. This allows the core to maintain the semaphore cache line in an exclusive state, which allows it to acquire the semaphore faster and to avoid transmitting that cache line to other cores unnecessarily.

公开(公告)号：US20180046463A1

公开(公告)日：2018-02-15

申请号：US15236882

申请日：2016-08-15

Applicant: Advanced Micro Devices, Inc.

Inventor： John M. King

IPC: G06F9/38 ,  G06F9/30

Abstract: A system and method for load queue (LDQ) and store queue (STQ) entry allocations at address generation time that maintains age-order of instructions is described. In particular, writing LDQ and STQ entries are delayed until address generation time. This allows the load and store operations to dispatch, and younger operations (which may not be store and load operations) to also dispatch and execute their instructions. The address generation of the load or store operation is held at an address generation scheduler queue (AGSQ) until a load or store queue entry is available for the operation. The tracking of load queue entries or store queue entries is effectively being done in the AGSQ instead of at the decode engine. The LDQ and STQ depth is not visible from a decode engine's perspective, and increases the effective processing and queue depth.

公开(公告)号：US20140244978A1

公开(公告)日：2014-08-28

申请号：US13781403

申请日：2013-02-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： John M. King

IPC: G06F9/30

CPC classification number: G06F9/384 ,  G06F9/30098 ,  G06F9/3857 ,  G06F9/3863

Abstract: The present invention provides a method and apparatus for checkpointing registers for transactional memory. Some embodiments of the apparatus include first rename logic configured to map up to a predetermined number of architectural registers to corresponding first physical registers that hold first values associated with the architectural registers. The mapping is responsive to a transaction modifying one or more of the first values associated with the architectural registers. Some embodiments of the apparatus also include microcode configured to write contents of the first physical registers to a memory in response to the transaction modifying first values associated with a number of the architectural registers that is larger than the predetermined number.

Abstract translation: 本发明提供了一种用于检查事件存储器的寄存器的方法和装置。 该装置的一些实施例包括第一重命名逻辑，其被配置为将高达预定数量的架构寄存器映射到相应的第一物理寄存器，该第一物理寄存器保存与架构寄存器相关联的第一值。 映射响应于修改与架构寄存器相关联的一个或多个第一值的事务。 该装置的一些实施例还包括被配置为响应于事务修改将第一物理寄存器的内容写入存储器的微代码，修改与多于该预定数量的多个架构寄存器相关联的第一值。

公开(公告)号：US12072803B1

公开(公告)日：2024-08-27

申请号：US17855681

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： John M. King

IPC: G06F12/08 ,  G06F9/30 ,  G06F12/0811 ,  G06F12/0891

CPC classification number: G06F12/0811 ,  G06F9/30043 ,  G06F12/0891 ,  G06F2212/1021

Abstract: The disclosed computer-implemented method for tracking miss requests using data cache tags can include generating a data cache miss request associated with data requested in connection with a cacheline and allocating a miss address buffer entry for the miss request. Additionally, the method can include, setting a fill-pending flag associated with the cacheline in response to the data associated with the data cache miss request being absent from a first data cache, and de-allocating the miss address buffer entry. In the event that another load or store operation requests the same data associated with the cacheline while the fill-pending flag is set, the method can include monitoring for a fill response associated with the miss request until the fill response is received. Upon receipt of the fill response, the method can include re-setting the fill-pending flag associated with the cacheline.

公开(公告)号：US11113056B2

公开(公告)日：2021-09-07

申请号：US16698808

申请日：2019-11-27

Applicant: Advanced Micro Devices, Inc.

Inventor： John M. King ,  Matthew T. Sobel

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/54 ,  G06F12/0811

Abstract: A technique for performing store-to-load forwarding is provided. The technique includes determining a virtual address for data to be loaded for the load instruction, identifying a matching store instruction from one or more store instruction memories by comparing a virtual-address-based comparison value for the load instruction to one or more virtual-address-based comparison values of one or more store instructions, determining a physical address for the load instruction, and validating the load instruction based on a comparison between the physical address of the load instruction and a physical address of the matching store instruction.

公开(公告)号：US20190187990A1

公开(公告)日：2019-06-20

申请号：US15846457

申请日：2017-12-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Gregory W. Smaus ,  John M. King

IPC: G06F9/30

CPC classification number: G06F9/30043 ,  G06F9/30145

Abstract: A system and method for a lightweight fence is described. In particular, micro-operations including a fencing micro-operation are dispatched to a load queue. The fencing micro-operation allows micro-operations younger than the fencing micro-operation to execute, where the micro-operations are related to a type of fencing micro-operation. The fencing micro-operation is executed if the fencing micro-operation is the oldest memory access micro-operation, where the oldest memory access micro-operation is related to the type of fencing micro-operation. The fencing micro-operation determines whether micro-operations younger than the fencing micro-operation have load ordering violations and if load ordering violations are detected, the fencing micro-operation signals the retire queue that instructions younger than the fencing micro-operation should be flushed. The instructions to be flushed should include all micro-operations with load ordering violations.

公开(公告)号：US10037283B2

公开(公告)日：2018-07-31

申请号：US15235214

申请日：2016-08-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Anthony J. Bybell ,  John M. King

IPC: G06F12/123 ,  G06F12/1027

CPC classification number: G06F12/1027 ,  G06F12/12 ,  G06F12/124 ,  G06F2212/1016 ,  G06F2212/684 ,  G06F2212/70

Abstract: Techniques for improving translation lookaside buffer (TLB) operation are disclosed. A particular entry of the TLB is to be updated with data associated with a large page size. The TLB updates replacement policy data for that TLB entry for that large page size to indicate that the TLB entry is not the least-recently-used. To prevent smaller pages from evicting the TLB entry for the large page size, the TLB also updates replacement policy data for that TLB entry for the smaller page size to indicate that the TLB entry is not the least-recently-used.

公开(公告)号：US20180181496A1

公开(公告)日：2018-06-28

申请号：US15389955

申请日：2016-12-23

Applicant: Advanced Micro Devices, Inc.

Inventor： John M. King ,  Michael T. Clark

IPC: G06F12/1027 ,  G06F12/122

CPC classification number: G06F12/1027 ,  G06F12/123 ,  G06F12/127 ,  G06F2212/1044 ,  G06F2212/303 ,  G06F2212/601 ,  G06F2212/652 ,  G06F2212/683 ,  G06F2212/684

Abstract: Methods, devices, and systems for determining an address in a physical memory which corresponds to a virtual address using a skewed-associative translation lookaside buffer (TLB) are described. A virtual address and a configuration indication are received using receiver circuitry. A physical address corresponding to the virtual address is output if a TLB hit occurs. A first subset of a plurality of ways of the TLB is configured to hold a first page size. The first subset includes a number of the ways based on the configuration indication. A physical address corresponding to the virtual address is retrieved from a page table if a TLB miss occurs, and at least a portion of the physical address is installed in a least recently used way of a subset of a plurality of ways the TLB, determined according to a replacement policy based on the configuration indication.