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    Scalable Cache Coherency Protocol
    21.
    发明申请
    Scalable Cache Coherency Protocol 有权

    公开(公告)号：US20230083397A1

    公开(公告)日：2023-03-16

    申请号：US18058105

    申请日：2022-11-22

    Applicant: Apple Inc.

    Inventor： James Vash ,  Gaurav Garg ,  Brian P. Lilly ,  Ramesh B. Gunna ,  Steven R. Hutsell ,  Lital Levy-Rubin ,  Per H. Hammarlund ,  Harshavardhan Kaushikkar

    IPC: G06F12/0815 ,  G06F12/0831

    Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.

    Scalable cache coherency protocol
    22.
    发明授权
    Scalable cache coherency protocol 有权

    公开(公告)号：US11544193B2

    公开(公告)日：2023-01-03

    申请号：US17315725

    申请日：2021-05-10

    Applicant: Apple Inc.

    Inventor： James Vash ,  Gaurav Garg ,  Brian P. Lilly ,  Ramesh B. Gunna ,  Steven R. Hutsell ,  Lital Levy-Rubin ,  Per H. Hammarlund ,  Harshavardhan Kaushikkar

    IPC: G06F12/0815 ,  G06F12/0831

    Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.

    Power Sense Correction for Power Budget Estimator
    23.
    发明申请
    Power Sense Correction for Power Budget Estimator 有权

    公开(公告)号：US20220342471A1

    公开(公告)日：2022-10-27

    申请号：US17812086

    申请日：2022-07-12

    Applicant: Apple Inc.

    Inventor： Matthias Knoth ,  Srikanth Balasubramanian ,  Venkatram Krishnaswamy ,  Ramesh B. Gunna

    IPC: G06F1/28 ,  G06Q50/06 ,  G06F1/3228

    Abstract: An apparatus includes an execute circuit configured to execute a plurality of operations received from a queue, as well as a power estimator circuit, and a power sensing circuit. The power estimator circuit is configured to predict power consumption due to execution of a particular operation of the plurality of operations, and to withdraw, based on the predicted power consumption, a first amount of power credits from a power credit pool. The power sensing circuit is configured to monitor one or more characteristics of a power supply node coupled to the execute circuit to generate a power value, and to deposit a second amount of power credits into the power credit pool. The second amount of power credits may be based on the power value indicating that power consumed during the execution of the particular operation is less than the predicted power consumption.

    Scalable cache coherency protocol
    27.
    发明授权
    Scalable cache coherency protocol 有权

    公开(公告)号：US11947457B2

    公开(公告)日：2024-04-02

    申请号：US18058105

    申请日：2022-11-22

    Applicant: Apple Inc.

    Inventor： James Vash ,  Gaurav Garg ,  Brian P. Lilly ,  Ramesh B. Gunna ,  Steven R. Hutsell ,  Lital Levy-Rubin ,  Per H. Hammarlund ,  Harshavardhan Kaushikkar

    IPC: G06F12/0815 ,  G06F12/0831

    CPC classification number: G06F12/0815 ,  G06F12/0831 ,  G06F2212/1032

    Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.

    Power sense correction for power budget estimator
    28.
    发明授权
    Power sense correction for power budget estimator 有权

    公开(公告)号：US11675409B2

    公开(公告)日：2023-06-13

    申请号：US17812086

    申请日：2022-07-12

    Applicant: Apple Inc.

    Inventor： Matthias Knoth ,  Srikanth Balasubramanian ,  Venkatram Krishnaswamy ,  Ramesh B. Gunna

    IPC: G06F1/28 ,  G06Q50/06 ,  G06F1/3228

    CPC classification number: G06F1/28 ,  G06F1/3228 ,  G06Q50/06

    Abstract: An apparatus includes an execute circuit configured to execute a plurality of operations received from a queue, as well as a power estimator circuit, and a power sensing circuit. The power estimator circuit is configured to predict power consumption due to execution of a particular operation of the plurality of operations, and to withdraw, based on the predicted power consumption, a first amount of power credits from a power credit pool. The power sensing circuit is configured to monitor one or more characteristics of a power supply node coupled to the execute circuit to generate a power value, and to deposit a second amount of power credits into the power credit pool. The second amount of power credits may be based on the power value indicating that power consumed during the execution of the particular operation is less than the predicted power consumption.

    Scalable Cache Coherency Protocol
    29.
    发明公开
    Scalable Cache Coherency Protocol 审中-公开

    公开(公告)号：US20230169003A1

    公开(公告)日：2023-06-01

    申请号：US18160575

    申请日：2023-01-27

    Applicant: Apple Inc.

    Inventor： James Vash ,  Gaurav Garg ,  Brian P. Lilly ,  Ramesh B. Gunna ,  Steven R. Hutsell ,  Lital Levy-Rubin ,  Per H. Hammarlund ,  Harshavardhan Kaushikkar

    IPC: G06F12/0815 ,  G06F12/0831

    CPC classification number: G06F12/0815 ,  G06F12/0831 ,  G06F2212/1032

    Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.

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