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    Testing an array of integrated circuits formed on a substrate sheet
    22.
    发明授权
    Testing an array of integrated circuits formed on a substrate sheet 有权

    公开(公告)号：US11243250B2

    公开(公告)日：2022-02-08

    申请号：US16483190

    申请日：2017-12-19

    Applicant: ARM LIMITED

    Inventor： James Edward Myers ,  John Philip Biggs ,  Jedrzej Kufel

    IPC: G01R31/317 ,  G01R31/3183 ,  H01L21/66 ,  H01L25/00

    Abstract: Integrated circuits (12) are manufactured by printing an array of circuit elements CE each containing an integrated circuit and associated testing circuitry (14). A plurality of integrated circuits within the array are tested in parallel to generate a corresponding plurality of individual test result signals. These individual test result signals are combined to form a combined test result signal indicating whether any of the plurality of integrated circuits tested in parallel operated incorrectly during their testing. If the combined test result signal indicates any faulty integrated circuits, then the entire plurality of integrated circuits (e.g. an entire row or column) may be discarded. The array of tested integrated circuits are then separated into discrete integrated circuits and are also separated from their testing circuit. Contacts (16, 18, 20) providing power signals, clock signals, and the reading of the combined test result signals are located at the periphery of a substrate sheet onto which the array of circuit elements are printed.

    Communication between voltage domains
    28.
    发明授权
    Communication between voltage domains 有权

    公开(公告)号：US09935634B2

    公开(公告)日：2018-04-03

    申请号：US14327004

    申请日：2014-07-09

    Applicant: ARM Limited

    Inventor： David Walter Flynn ,  James Edward Myers

    IPC: H03K19/01 ,  H03K19/0175

    CPC classification number: H03K19/017509

    Abstract: An integrated circuit including a first voltage domain incorporates real time clock circuitry that communicates via communication circuitry with processing circuitry contained within a second voltage domain. The communication circuitry includes first parallel-to-serial conversion circuitry located within the first voltage domain, level shifting circuitry for passing serial signals between the voltage domains and second parallel-to-serial circuitry located in the second voltage domain.

    Power gating in an electronic device
    29.
    发明授权
    Power gating in an electronic device 有权

    公开(公告)号：US09720434B2

    公开(公告)日：2017-08-01

    申请号：US14731250

    申请日：2015-06-04

    Applicant: ARM Limited

    Inventor： James Edward Myers ,  David Walter Flynn ,  David William Howard

    IPC: H03K19/0175 ,  G05F3/08 ,  G06F17/50 ,  G06F1/32 ,  H03K19/00

    CPC classification number: G05F3/08 ,  G06F1/26 ,  G06F1/3287 ,  G06F17/5068 ,  H03K19/0016 ,  Y02D10/171

    Abstract: An electronic device 2 has circuitry 4 which operates in a first voltage domain 6 supplied with a first voltage level VDD1 and a reference voltage level. A voltage regulator 14 generates the first voltage level VDD1 from a second voltage level VDD2 higher than the first voltage level VDD1. At least one power gate 20, 30 is provided for selectively coupling the circuitry 4 to one of the first voltage level VDD1 or the reference level. The control signal 22 for the power gate 20, 30 is generated in a second voltage domain supplied with a higher voltage level VDD2 or VDD3 derived from the second voltage level VDD2 supplied to the voltage regulator 14. Hence, an existing high voltage source within the device 2 can be reused for applying a boosted voltage to power gates to improve efficiency of power gating.

    Controlling voltage generation and voltage comparison
    30.
    发明授权
    Controlling voltage generation and voltage comparison 有权
    控制电压产生和电压比较

    公开(公告)号：US09170282B2

    公开(公告)日：2015-10-27

    申请号：US13895624

    申请日：2013-05-16

    Applicant: ARM LIMITED

    Inventor： Parameshwarappa Anand Kumar Savanth ,  James Edward Myers ,  David Walter Flynn ,  Bal S. Sandhu

    IPC: H03K19/094 ,  G01R19/00 ,  H02M3/07

    CPC classification number: H02M3/157 ,  G01R19/0084 ,  H02M3/07 ,  Y02B70/16

    Abstract: An integrated circuit has voltage generating circuitry for generating an on-chip voltage from a supply voltage in response to clock pulses. Clock control circuitry controls transmission of the clock pulses to the voltage generating circuitry. The clock control circuitry receives a reference voltage and a digital offset value comprising a binary numeric value identifying an offset. The clock control circuitry suppresses transmission of the clock pulses if the on-chip voltage is greater than the sum of the reference voltage and the offset identified by the digital offset value, to reduce power consumption. The offset can be tuned digitally to vary the average level of the on-chip voltage. A similar digital tuning mechanism may be used in a clocked comparator to compare a first voltage with a digitally tunable threshold voltage.

    Abstract translation: 集成电路具有用于响应于时钟脉冲从电源电压产生片上电压的电压产生电路。 时钟控制电路控制时钟脉冲的传输到电压产生电路。 时钟控制电路接收参考电压和包括识别偏移的二进制数值的数字偏移值。 如果片上电压大于参考电压和由数字偏移值识别的偏移的总和，则时钟控制电路抑制时钟脉冲的传输，以减少功耗。 可以数字调整偏移量以改变片内电压的平均电平。 在时钟控制的比较器中可以使用类似的数字调谐机构来将第一电压与数字可调阈值电压进行比较。

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