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公开(公告)号：US09940993B2
公开(公告)日：2018-04-10
申请号：US15093457
申请日：2016-04-07
Applicant: ARM Limited
Inventor： Parameshwarappa Anand Kumar Savanth , James Edward Myers , Pranay Prabhat , David Walter Flynn , Shidhartha Das , David Michael Bull
IPC: G11C5/06 , G11C11/419
CPC classification number: G11C11/419 , G11C5/063 , G11C11/4125
Abstract: A storage bitcell comprising a first inverter cross-coupled with a second inverter, both the first and second inverter being in a path between a first potential and a second potential; wherein a first isolator is connected in the path between the first inverter and the first potential. The storage bitcell has particular application as Static Random-Access Memory (SRAM) circuitry.
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公开(公告)号：US20240220395A1
公开(公告)日：2024-07-04
申请号：US18554773
申请日：2022-02-10
Applicant: Arm Limited
Inventor： Parameshwarappa Anand Kumar Savanth , Sahan Sajeewa Hiniduma Udugama Gamage , Wei Wang , Andreas Lars Sandberg
IPC: G06F11/36
CPC classification number: G06F11/3636 , G06F11/3656
Abstract: An apparatus and method are described for generating debug information. The apparatus has processing circuitry for executing a sequence of instructions that includes a plurality of debug information triggering instructions, and debug information generating circuitry for coupling to a debug port. On executing a given debug information triggering instruction, the processing circuitry is arranged to trigger the debug information generating circuitry to generate a debug information signal whose form is dependent on a control parameter specified by the given debug information triggering instruction. The generated debug information signal is output from the debug port for reference by a debugger. The control parameter is such that the form of the debug information signal enables the debugger to determine a state of the processing circuitry when the given debug information triggering instruction was executed.
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公开(公告)号：US11620485B2
公开(公告)日：2023-04-04
申请号：US16898085
申请日：2020-06-10
Applicant: Arm Limited
Inventor： James Edward Myers , Ludmila Cherkasova , Parameshwarappa Anand Kumar Savanth , Sahan Sajeewa Hiniduma Udugama Gamage , Mbou Eyole
IPC: G06K19/07
Abstract: Disclosed are methods, systems and devices for varying operations of a transponder device based, at least in part, on an availability of energy and/or power that may be harvested and/or collected. In one particular implementation, operations to generate one or more signals from sensor circuitry and/or to perform computations may be varied based, at least in part, on an availability of harvestable and/or collectable energy and/or power.
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公开(公告)号：US11589261B2
公开(公告)日：2023-02-21
申请号：US17207455
申请日：2021-03-19
Applicant: Arm Limited
Inventor： Sahan Sajeewa Hiniduma Udugama Gamage , Parameshwarappa Anand Kumar Savanth , Jedrzej Kufel , Mbou Eyole
Abstract: Subject matter disclosed herein may relate to reconstructing wireless signal packets and may relate more particularly to reconstructing wireless signal packets from iterations of the wireless signal packets repeatedly transmitted by a transmitter device.
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公开(公告)号：US20210365092A1
公开(公告)日：2021-11-25
申请号：US16882402
申请日：2020-05-22
Applicant: Arm Limited
Abstract: Various implementations described herein are related to a device having energy harvesting circuitry that experiences power failures. The device may include computing circuitry having a processor coupled to the energy harvesting circuitry. The processor may be configured to reduce a number of write operations to a log structure having a hardware bit-vector used by the computing circuitry to boost computational progress even with the power failures.
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Patent Agency Ranking
公开(公告)号：US10903822B2
公开(公告)日：2021-01-26
申请号：US16293518
申请日：2019-03-05
Applicant: Arm Limited
Inventor： Philex Ming-Yan Fan , Parameshwarappa Anand Kumar Savanth , Benoit Labbe , Bal S. Sandhu , Pranay Prabhat , James Edward Myers
IPC: H03K3/0231 , H02M3/07 , H03K19/20
Abstract: Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has a step-down converter coupled to an oscillator between a first voltage supply and a second voltage supply. The second stage is coupled to the first stage, and the second stage has a current bias generator coupled to a diode-connected transistor between the first voltage supply and the second voltage supply. The second stage provides an intermediate voltage to the first stage.
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公开(公告)号：US20200287524A1
公开(公告)日：2020-09-10
申请号：US16293518
申请日：2019-03-05
Applicant: Arm Limited
Inventor： Philex Ming-Yan Fan , Parameshwarappa Anand Kumar Savanth , Benoit Labbe , Bal S. Sandhu , Pranay Prabhat , James Edward Myers
IPC: H03K3/0231 , H02M3/07
Abstract: Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has a step-down converter coupled to an oscillator between a first voltage supply and a second voltage supply. The second stage is coupled to the first stage, and the second stage has a current bias generator coupled to a diode-connected transistor between the first voltage supply and the second voltage supply. The second stage provides an intermediate voltage to the first stage.
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公开(公告)号：US20200035668A1
公开(公告)日：2020-01-30
申请号：US16044231
申请日：2018-07-24
Applicant: Arm Limited , The Regents of the University of Michigan
Inventor： Parameshwarappa Anand Kumar Savanth , Fabrice Blanc , David Theodore Blaauw , Sechang Oh , In Hee Lee
Abstract: In a particular implementation, an apparatus to control clamping devices includes a first control circuit and a second control circuit. The first control circuit is responsive to a detection signal and generates a first drive signal to control a body diode of a clamping device. The second control circuit is responsive to the detection signal and generates a second drive signal to control the gate terminal of the clamping device.
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公开(公告)号：US20180219549A1
公开(公告)日：2018-08-02
申请号：US15418331
申请日：2017-01-27
Applicant: ARM Limited
IPC: H03K17/687
CPC classification number: H03K17/6872 , H01L29/1087 , H03K17/04163 , H03K19/00 , H03K19/0013 , H03K2217/0018 , H03K2217/0036
Abstract: Embodiments are described for digital forward body biasing CMOS circuits. In an embodiment, a power management unit limits the amount of time for which digital forward body biasing may be implemented. In another embodiment, once a CMOS circuit is put into a full digital forward body bias mode, the CMOS circuit is gradually brought back to a zero forward body bias mode. In another embodiment, charge is shared among biased transistor wells during transition intervals when transitioning from one bias mode to another.
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公开(公告)号：US09170282B2
公开(公告)日：2015-10-27
申请号：US13895624
申请日：2013-05-16
Applicant: ARM LIMITED
Inventor： Parameshwarappa Anand Kumar Savanth , James Edward Myers , David Walter Flynn , Bal S. Sandhu
IPC: H03K19/094 , G01R19/00 , H02M3/07
CPC classification number: H02M3/157 , G01R19/0084 , H02M3/07 , Y02B70/16
Abstract: An integrated circuit has voltage generating circuitry for generating an on-chip voltage from a supply voltage in response to clock pulses. Clock control circuitry controls transmission of the clock pulses to the voltage generating circuitry. The clock control circuitry receives a reference voltage and a digital offset value comprising a binary numeric value identifying an offset. The clock control circuitry suppresses transmission of the clock pulses if the on-chip voltage is greater than the sum of the reference voltage and the offset identified by the digital offset value, to reduce power consumption. The offset can be tuned digitally to vary the average level of the on-chip voltage. A similar digital tuning mechanism may be used in a clocked comparator to compare a first voltage with a digitally tunable threshold voltage.
Abstract translation: 集成电路具有用于响应于时钟脉冲从电源电压产生片上电压的电压产生电路。 时钟控制电路控制时钟脉冲的传输到电压产生电路。 时钟控制电路接收参考电压和包括识别偏移的二进制数值的数字偏移值。 如果片上电压大于参考电压和由数字偏移值识别的偏移的总和，则时钟控制电路抑制时钟脉冲的传输，以减少功耗。 可以数字调整偏移量以改变片内电压的平均电平。 在时钟控制的比较器中可以使用类似的数字调谐机构来将第一电压与数字可调阈值电压进行比较。
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