公开(公告)号：US20090001430A1

公开(公告)日：2009-01-01

申请号：US11771013

申请日：2007-06-29

申请人： Ashima B. Chakravarti ,  Renee T. Mo

发明人： Ashima B. Chakravarti ,  Renee T. Mo

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/823481 ,  H01L21/28176 ,  H01L29/66636 ,  H01L29/7848

摘要： A dielectric element, and method of manufacturing the same, is disclosed for a semiconductor structure which comprises a substrate having a gate formed on a top surface of the substrate. The substrate and gate define a gap in a region between the gate and the substrate. A specified amount of dielectric on the substrate, at least a portion of which is in the gap, forms the dielectric element which substantially prevents unwanted electrical connectivity between the gate and the substrate.

摘要翻译： 公开了一种用于半导体结构的电介质元件及其制造方法，该半导体结构包括在衬底的顶表面上形成有栅极的衬底。 衬底和栅极限定栅极和衬底之间的区域中的间隙。 衬底上的至少一部分位于间隙中的指定量的电介质形成基本上防止栅极和衬底之间不必要的电连接的电介质元件。

公开(公告)号：US07361611B2

公开(公告)日：2008-04-22

申请号：US11349233

申请日：2006-02-08

申请人： Ashima B. Chakravarti ,  Judson Holt ,  Kevin K. Chan ,  Sadanand V. Deshpande ,  Rangarajan Jagannathan

发明人： Ashima B. Chakravarti ,  Judson Holt ,  Kevin K. Chan ,  Sadanand V. Deshpande ,  Rangarajan Jagannathan

IPC分类号： H01L21/31

CPC分类号： H01L29/7843 ,  C23C16/308 ,  C23C16/34 ,  C23C16/401 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/3143 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/3148 ,  H01L21/31608 ,  H01L21/31612 ,  H01L21/3185 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76834 ,  H01L29/7833 ,  H01L29/78675

摘要： Adding at least one non-silicon precursor (such as a germanium precursor, a carbon precursor, etc.) during formation of a silicon nitride, silicon oxide, silicon oxynitride or silicon carbide film improves the deposition rate and/or makes possible tuning of properties of the film, such as tuning of the stress of the film. Also, in a doped silicon oxide or doped silicon nitride or other doped structure, the presence of the dopant may be used for measuring a signal associated with the dopant, as an etch-stop or otherwise for achieving control during etching.

摘要翻译： 在形成氮化硅，氧化硅，氮氧化硅或碳化硅膜期间添加至少一种非硅前体（例如锗前体，碳前体等）改善了沉积速率和/或使得可以调谐性能 的电影，如调整电影的压力。 此外，在掺杂的氧化硅或掺杂氮化硅或其它掺杂结构中，掺杂剂的存在可用于测量与掺杂剂相关的信号，作为蚀刻停止或用于在蚀刻期间实现控制。

公开(公告)号：US07119016B2

公开(公告)日：2006-10-10

申请号：US10684596

申请日：2003-10-15

申请人： Ashima B. Chakravarti ,  Anita Madan ,  Woo-Hyeong Lee ,  Gregory Wayne Dibello ,  Ramaseshan Suryanarayanan Iyer

发明人： Ashima B. Chakravarti ,  Anita Madan ,  Woo-Hyeong Lee ,  Gregory Wayne Dibello ,  Ramaseshan Suryanarayanan Iyer

IPC分类号： H01L21/36

CPC分类号： C23C16/36 ,  C23C16/24 ,  H01L21/02532 ,  H01L21/0262

摘要： A compound that includes at least Si, N and C in any combination, such as compounds of formula (R—NH)4-nSiXn wherein R is an alkyl group (which may be the same or different), n is 1, 2 or 3, and X is H or halogen (such as, e.g., bis-tertiary butyl amino silane (BTBAS)), may be mixed with silane or a silane derivative to produce a film. A polysilicon silicon film may be grown by mixing silane (SiH4) or a silane derviative and a compound including Si, N and C, such as BTBAS. Films controllably doped with carbon and/or nitrogen (such as layered films) may be grown by varying the reagents and conditions.

摘要翻译： 至少包含任何组合中的Si，N和C的化合物，例如式（R-NH）4-n-SiX n N的化合物，其中R是烷基 （其可以相同或不同），n为1,2或3，X为H或卤素（例如双叔丁基氨基硅烷（BTBAS））可与硅烷或硅烷衍生物混合 制作一部电影。 可以通过混合硅烷（SiH 4 SO 4）或硅烷衍生物和包括Si，N和C的化合物如BTBAS来生长多晶硅硅膜。 可以通过改变试剂和条件来生长可控地掺杂有碳和/或氮的膜（例如层状膜）。

公开(公告)号：US08563446B2

公开(公告)日：2013-10-22

申请号：US13474790

申请日：2012-05-18

申请人： Ashima B. Chakravarti ,  Jacob B. Dadson ,  Paul J. Higgins ,  Babar A. Khan ,  John J. Moore ,  Christopher C. Parks ,  Rohit S. Takalkar

发明人： Ashima B. Chakravarti ,  Jacob B. Dadson ,  Paul J. Higgins ,  Babar A. Khan ,  John J. Moore ,  Christopher C. Parks ,  Rohit S. Takalkar

IPC分类号： H01L29/02

CPC分类号： H01L27/10867 ,  H01L29/66181 ,  H01L29/945 ,  Y10S438/957

摘要： A method for forming a trench structure is provided for a semiconductor and/or memory device, such as an DRAM device. In one embodiment, the method for forming a trench structure includes forming a trench in a semiconductor substrate, and exposing the sidewalls of the trench to an arsenic-containing gas to adsorb an arsenic containing layer on the sidewalls of the trench. A material layer is then deposited on the sidewalls of the trench to encapsulate the arsenic-containing layer between the material layer and sidewalls of the trench.

摘要翻译： 为诸如DRAM器件的半导体和/或存储器件提供了用于形成沟槽结构的方法。 在一个实施例中，用于形成沟槽结构的方法包括在半导体衬底中形成沟槽，并且将沟槽的侧壁暴露于含砷气体以在沟槽的侧壁上吸附含砷层。 然后将材料层沉积在沟槽的侧壁上以将含砷层包封在材料层和沟槽的侧壁之间。

公开(公告)号：US20100112762A1

公开(公告)日：2010-05-06

申请号：US12684551

申请日：2010-01-08

申请人： Thomas N. Adam ,  Ashima B. Chakravarti ,  Eric C.T. Harley ,  Judson R. Holt

发明人： Thomas N. Adam ,  Ashima B. Chakravarti ,  Eric C.T. Harley ,  Judson R. Holt

IPC分类号： H01L21/336 ,  H01L21/20

CPC分类号： H01L29/66545 ,  H01L21/0237 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/76224 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66553

摘要： Methods of fabricating a semiconductor structure with a non- epitaxial thin film disposed on a surface of a substrate of the semiconductor structure are disclosed. The methods provide selective non-epitaxial growth (SNEG) or deposition of amorphous and/or polycrystalline materials to form a thin film on the surface thereof. The surface may be a non-crystalline dielectric material or a crystalline material. The SNEG on non-crystalline dielectric further provides selective growth of amorphous/polycrystalline materials on nitride over oxide through careful selection of precursors-carrier-etchant ratio. The non-epitaxial thin film forms resultant and/or intermediate semiconductor structures that may be incorporated into any front-end-of-the-line (FEOL) fabrication process. Such resultant/intermediate structures may be used, for example, but are not limited to: source-drain fabrication; hardmask strengthening; spacer widening; high-aspect-ratio (HAR) vias filling; micro-electro-mechanical-systems (MEMS) fabrication; FEOL resistor fabrication; lining of shallow trench isolations (STI) and deep trenches; critical dimension (CD) tailoring and claddings.

摘要翻译： 公开了制造具有设置在半导体结构的衬底的表面上的非外延薄膜的半导体结构的方法。 该方法提供非晶和/或多晶材料的选择性非外延生长（SNEG）或沉积以在其表面上形成薄膜。 表面可以是非结晶介电材料或结晶材料。 非结晶电介质上的SNEG还通过仔细选择前体载体 - 蚀刻剂比例，进一步提供非晶/多晶材料对氧化物上的氮化物的选择性生长。 非外延薄膜形成可并入到任何前端（FEOL）制造工艺中的所得和/或中间半导体结构。 这样的合成/中间结构可以用于例如但不限于：源极 - 漏极制造; 硬掩模强化; 间隔加宽; 高纵横比（HAR）通孔填充; 微电子机械系统（MEMS）制造; FEOL电阻制造; 浅沟槽隔离（STI）和深沟槽衬砌; 临界尺寸（CD）裁剪和包层。

公开(公告)号：US07595010B2

公开(公告)日：2009-09-29

申请号：US11924825

申请日：2007-10-26

申请人： Ashima B. Chakravarti ,  Judson Holt ,  Kevin K. Chan ,  Sadanand V. Deshpande ,  Rangarajan Jagannathan

发明人： Ashima B. Chakravarti ,  Judson Holt ,  Kevin K. Chan ,  Sadanand V. Deshpande ,  Rangarajan Jagannathan

IPC分类号： H01B1/00

CPC分类号： H01L29/7843 ,  C23C16/308 ,  C23C16/34 ,  C23C16/401 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/3143 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/3148 ,  H01L21/31608 ,  H01L21/31612 ,  H01L21/3185 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76834 ,  H01L29/7833 ,  H01L29/78675

摘要： Adding at least one non-silicon precursor (such as a germanium precursor, a carbon precursor, etc.) during formation of a silicon nitride, silicon oxide, silicon oxynitride or silicon carbide film improves the deposition rate and/or makes possible tuning of properties of the film, such as tuning of the stress of the film. Also, in a doped silicon oxide or doped silicon nitride or other doped structure, the presence of the dopant may be used for measuring a signal associated with the dopant, as an etch-stop or otherwise for achieving control during etching.

摘要翻译： 在形成氮化硅，氧化硅，氮氧化硅或碳化硅膜期间添加至少一种非硅前体（例如锗前体，碳前体等）改善了沉积速率和/或使得可以调谐性能 的电影，如调整电影的压力。 此外，在掺杂的氧化硅或掺杂氮化硅或其它掺杂结构中，掺杂剂的存在可用于测量与掺杂剂相关的信号，作为蚀刻停止或用于在蚀刻期间实现控制。

公开(公告)号：US07001844B2

公开(公告)日：2006-02-21

申请号：US10835949

申请日：2004-04-30

申请人： Ashima B. Chakravarti ,  Shreesh Narasimha ,  Victor Chan ,  Judson Holt ,  Satya N. Chakravarti

发明人： Ashima B. Chakravarti ,  Shreesh Narasimha ,  Victor Chan ,  Judson Holt ,  Satya N. Chakravarti

IPC分类号： H01L21/469

CPC分类号： H01L21/0217 ,  C23C16/345 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/3185 ,  H01L29/7843

摘要： Stress level of a nitride film is adjusted as a function of two or more of the following: identity of a starting material precursor used to make the nitride film; identity of a nitrogen-containing precursor with which is treated the starting material precursor; ratio of the starting material precursor to the nitrogen-containing precursor; a set of CVD conditions under which the film is grown; and/or a thickness to which the film is grown. A rapid thermal chemical vapor deposition (RTCVD) film produced by reacting a compound containing silicon, nitrogen and carbon (such as bis-tertiary butyl amino silane (BTBAS)) with NH3 can provide advantageous properties, such as high stress and excellent performance in an etch-stop application. An ammonia-treated BTBAS film is particularly excellent in providing a high-stress property, and further having maintainability of that high-stress property over repeated annealing.

公开(公告)号：US06838695B2

公开(公告)日：2005-01-04

申请号：US10304163

申请日：2002-11-25

申请人： Bruce B. Doris ,  Ashima B. Chakravarti ,  Kevin K. Chan ,  Daniel A. Uriarte

发明人： Bruce B. Doris ,  Ashima B. Chakravarti ,  Kevin K. Chan ,  Daniel A. Uriarte

IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/04

CPC分类号： H01L29/4925 ,  H01L21/28044 ,  H01L21/823842

摘要： A semiconductor device structure includes a substrate, a dielectric layer disposed on the substrate, first and second stacks disposed on the dielectric layer. The first stack includes a first silicon layer disposed on the dielectric layer, a silicon germanium layer disposed on the first silicon layer, a second silicon layer disposed on the silicon germanium layer, and a third silicon layer disposed on the second silicon layer. The second stack includes a first silicon layer disposed on the dielectric layer, and a second silicon layer disposed on the first silicon layer. Alternatively, the silicon germanium layer includes Boron.

摘要翻译： 半导体器件结构包括衬底，设置在衬底上的电介质层，设置在电介质层上的第一和第二堆叠。 第一堆叠包括设置在电介质层上的第一硅层，设置在第一硅层上的硅锗层，设置在硅锗层上的第二硅层和设置在第二硅层上的第三硅层。 第二堆叠包括布置在电介质层上的第一硅层和设置在第一硅层上的第二硅层。 或者，硅锗层包括硼。

公开(公告)号：US06555166B2

公开(公告)日：2003-04-29

申请号：US09895378

申请日：2001-06-29

申请人： Oleg Gluschenkov ,  Ashima B. Chakravarti

发明人： Oleg Gluschenkov ,  Ashima B. Chakravarti

IPC分类号： C23C1600

CPC分类号： C23C16/45502 ,  C23C16/455

摘要： A method is provided for reducing the microloading effect in a CVD process for depositing a film on a substrate. This method is particularly useful in a single-wafer CVD reactor. The microloading effect is reduced by identifying a growth-rate-limiting reactant; calculating a dilution factor (the ratio of the gas flow rate of the growth-rate-limiting reactant to the total gas flow rate in the reactor); and adjusting the film growth rate and/or the dilution factor to satisfy a numerical criterion for reducing the microloading effect. The criterion is satisfied when the film growth rate is reduced, or the dilution factor is increased, so that the dilution factor is equal to or greater than a quantity which includes the film growth rate as a factor. The film growth rate and dilution factor may be adjusted independently. The gap between the showerhead and the substrate in the CVD reactor may be adjusted to satisfy the numerical criterion. The gap may advantageously be reduced to less than 5 mm, preferably to about 100 &mgr;m. A gap in the range 50 &mgr;m-5 mm reduces a characteristic distance which is a factor in the above-mentioned quantity, so that the criterion becomes easier to meet.

公开(公告)号：US6030881A

公开(公告)日：2000-02-29

申请号：US72759

申请日：1998-05-05

申请人： George D. Papasouliotis ,  Ashima B. Chakravarti ,  Richard A. Conti ,  Laertis Economikos ,  Patrick A. Van Cleemput

发明人： George D. Papasouliotis ,  Ashima B. Chakravarti ,  Richard A. Conti ,  Laertis Economikos ,  Patrick A. Van Cleemput

IPC分类号： C23C16/04 ,  C23C16/40 ,  C23C16/56 ,  H01L21/762

CPC分类号： H01L21/76224 ,  C23C16/045 ,  C23C16/401 ,  C23C16/56

摘要： A method is provided for filling high aspect ratio gaps without void formation by using a high density plasma (HDP) deposition process with a sequence of deposition and etch steps having varying etch rate-to-deposition rate (etch/dep) ratios. The first step uses an etch/dep ratio less than one to quickly fill the gap. The first step is interrupted before the opening to the gap is closed. The second step uses an etch/dep ratio greater than one to widen the gap. The second step is stopped before corners of the elements forming the gaps are exposed. These steps can be repeated until the aspect ratio of the gap is reduced so that void-free gap-fill is possible. The etch/dep ratio and duration of each step can be optimized for high throughput and high aspect ratio gap-fill capacity.

摘要翻译： 提供了一种通过使用具有不同蚀刻速率 - 沉积速率（蚀刻/去除）比率的沉积和蚀刻步骤顺序的高密度等离子体（HDP）沉积工艺来填充高纵横比间隙而无空隙形成的方法。 第一步使用小于1的蚀刻/剥离比快速填充间隙。 第一步在打开间隙之前中断。 第二步使用大于1的蚀刻/剥离比来扩大间隙。 在形成间隙的元件的角部暴露之前停止第二步骤。 可以重复这些步骤，直到间隙的纵横比减小，使得无空隙间隙填充成为可能。 可以优化每个步骤的蚀刻/剥离比和持续时间，以实现高通量和高纵横比填充间隙。