公开(公告)号：US20180107598A1

公开(公告)日：2018-04-19

申请号：US15295025

申请日：2016-10-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Andreas Prodromou ,  Mitesh R. Meswani ,  Arkaprava Basu ,  Nuwan S. Jayasena ,  Gabriel H. Loh

IPC: G06F12/0811

CPC classification number: G06F12/0811 ,  G06F9/5027

Abstract: Cluster manager functional blocks perform operations for migrating pages in portions in corresponding migration clusters. During operation, each cluster manager keeps an access record that includes information indicating accesses of pages in the portions in the corresponding migration cluster. Based on the access record and one or more migration policies, each cluster manager migrates pages between the portions in the corresponding migration cluster.

公开(公告)号：US20180069767A1

公开(公告)日：2018-03-08

申请号：US15257286

申请日：2016-09-06

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Joseph L. Greathouse ,  Guru Prasadh V. Venkataramani ,  Jan Vesely

IPC: H04L12/24 ,  H04L29/08 ,  G06F12/0817 ,  G06F9/50

CPC classification number: G06F12/0828 ,  G06F9/5011 ,  G06F9/5083 ,  G06F2209/504

Abstract: Techniques described herein improve processor performance in situations where a large number of system service requests are being received from other devices. More specifically, upon detecting that certain operating conditions that indicate a processor slowdown are present, the processor performs one or more system service adjustment techniques. These techniques include throttling (reducing the rate of handling) of such requests, coalescing (grouping multiple requests into a single group) the requests, disabling microarchitctural structures (such as caches or branch prediction units) or updates to those structures, and prefetching data for or pre-performing these requests. Each of these adjustment techniques helps to reduce the number of and/or workload associated with servicing requests for system services.

公开(公告)号：US20170371720A1

公开(公告)日：2017-12-28

申请号：US15191355

申请日：2016-06-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Dmitri Yudanov ,  David A. Roberts ,  Mitesh R. Meswani ,  Sergey Blagodurov

IPC: G06F9/52

Abstract: A method and processing apparatus for accelerating program processing is provided that includes a plurality of processors configured to process a plurality of tasks of a program and a controller. The controller is configured to determine, from the plurality of tasks being processed by the plurality of processors, a task being processed on a first processor to be a lagging task causing a delay in execution of one or more other tasks of the plurality of tasks. The controller is further configured to provide the determined lagging task to a second processor to be executed by the second processor to accelerate execution of the lagging task.

公开(公告)号：US20170168546A1

公开(公告)日：2017-06-15

申请号：US14963352

申请日：2015-12-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Mitesh R. Meswani ,  David A. Roberts ,  Dmitri Yudanov ,  Arkaprava Basu ,  Sergey Blagodurov

IPC: G06F1/32 ,  G06F1/28

CPC classification number: G06F1/3243 ,  G06F9/3885

Abstract: A method and apparatus for performing inter-lane power management includes de-energizing one or more execution lanes upon a determination that the one or more execution lanes are to be predicated. Energy from the predicated execution lanes is redistributed to one or more active execution lanes.

公开(公告)号：US11275613B2

公开(公告)日：2022-03-15

申请号：US15954382

申请日：2018-04-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Joseph Lee Greathouse

IPC: G06F9/46 ,  G06F9/48

Abstract: Systems, apparatuses, and methods for enforcing processor quality of service guarantees when servicing system service requests (SSRs) are disclosed. A system includes a first processor executing an operating system and a second processor executing an application which generates SSRs for the first processor to service. The first processor monitors the number of cycles spent servicing SSRs over a previous time interval, and if this number of cycles is above a threshold, the first processor starts delaying the servicing of subsequent SSRs. In one implementation, if the previous delay was non-zero, the first processor increases the delay used in the servicing of subsequent SSRs. If the number of cycles is less than or equal to the threshold, then the first processor services SSRs without delay. As the delay is increased, the second processor begins to stall and its SSR generation rate falls, reducing the load on the first processor.

公开(公告)号：US11144473B2

公开(公告)日：2021-10-12

申请号：US16007027

申请日：2018-06-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Michael LeBeane ,  Eric Van Tassell

IPC: G06F12/1036 ,  G06F12/1009 ,  G06F9/50 ,  G06F9/48 ,  G06F13/16 ,  G06F13/22

Abstract: A data processing system includes a memory, a group of input/output (I/O) devices, an input/output memory management unit (IOMMU). The IOMMU is connected to the memory and adapted to allocate a hardware resource from among a group of hardware resources to receive an address translation request for a memory access from an I/O device. The IOMMU detects address translation requests from the plurality of I/O devices. The IOMMU reorders the address translation requests such that an order of dispatching an address translation request is based on a policy associated with the I/O device that is requesting the memory access. The IOMMU selectively allocates a hardware resource to the input/output device, based on the policy that is associated with the I/O device in response to the reordering.

公开(公告)号：US10078588B2

公开(公告)日：2018-09-18

申请号：US15081379

申请日：2016-03-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Mark H. Oskin ,  Gabriel H. Loh ,  Andrew G. Kegel ,  David S. Christie ,  Kevin J. McGrath

IPC: G06F12/08 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0891 ,  G06F12/1027

CPC classification number: G06F12/0808 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0891 ,  G06F12/1027 ,  G06F2212/1024 ,  G06F2212/657 ,  G06F2212/683 ,  G06F2212/684 ,  Y02D10/13

Abstract: The described embodiments include a computing device with two or more translation lookaside buffers (TLB) that performs operations for handling entries in the TLBs. During operation, the computing device maintains lease values for entries in the TLBs, the lease values representing times until leases for the entries expire, wherein a given entry in the TLB is invalid when the associated lease has expired. The computing device uses the lease value to control operations that are allowed to be performed using information from the entries in the TLBs. In addition, the computing device maintains, in a page table, longest lease values for page table entries indicating when corresponding longest leases for entries in TLBs expire. The longest lease values are used to determine when and if a TLB shootdown is to be performed.

公开(公告)号：US10019377B2

公开(公告)日：2018-07-10

申请号：US15162464

申请日：2016-05-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Bradford M. Beckmann ,  Shuai Che ,  Sooraj Puthoor

IPC: G06F12/1009 ,  G06F12/0837 ,  G06F12/14 ,  G06F12/0817 ,  G06F12/1027

CPC classification number: G06F12/1009 ,  G06F12/0817 ,  G06F12/0837 ,  G06F12/1027 ,  G06F12/1483 ,  G06F2212/1024 ,  G06F2212/1052 ,  G06F2212/621 ,  G06F2212/657 ,  Y02D10/13

Abstract: The described embodiments include a computing device with two or more types of processors and a memory that is shared between the two or more types of processors. The computing device performs operations for handling cache coherency between the two or more types of processors. During operation, the computing device sets a cache coherency indicator in metadata in a page table entry in a page table, the page table entry information about a page of data that is stored in the memory. The computing device then uses the cache coherency indicator to determine operations to be performed when accessing data in the page of data in the memory. For example, the computing device can use the coherency indicator to determine whether a coherency operation is to be performed when a processor of a given type accesses data in the page of data in the memory.

公开(公告)号：US10019283B2

公开(公告)日：2018-07-10

申请号：US14746601

申请日：2015-06-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Dmitri Yudanov ,  Sergey Blagodurov ,  Arkaprava Basu ,  Sooraj Puthoor ,  Joseph L. Greathouse

IPC: G06F9/46 ,  G06F9/30

CPC classification number: G06F9/461 ,  G06F9/3013 ,  G06F9/3851

Abstract: A processing device includes a first memory that includes a context buffer. The processing device also includes a processor core to execute threads based on context information stored in registers of the processor core and a memory controller to selectively move a subset of the context information between the context buffer and the registers based on one or more latencies of the threads.