公开(公告)号：US20210057352A1

公开(公告)日：2021-02-25

申请号：US16544021

申请日：2019-08-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Rahul Agarwal ,  Milind S. Bhagavat ,  Priyal Shah ,  Chia-Hao Cheng ,  Brett P. Wilkerson ,  Lei Fu

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package is provided that includes a fan-out redistribution layer (RDL) structure that has plural stacked polymer layers, plural metallization layers, plural conductive vias interconnecting adjacent metallization layers of the metallization layers, and plural rivets configured to resist delamination of one or more of the polymer layers. Each of the plural rivets includes a first head, a second head and a shank connected between the first head and the second head. The first head is part of one of the metallization layers. The shank includes at least one of the conductive vias and at least one part of another of the metallization layers.

公开(公告)号：US20210020459A1

公开(公告)日：2021-01-21

申请号：US16513450

申请日：2019-07-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Priyal Shah ,  Milind S. Bhagavat ,  Brett P. Wilkerson ,  Lei Fu ,  Rahul Agarwal

IPC: H01L21/56 ,  H01L23/31

Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package includes a package substrate that has a first side and a second side opposite to the first side. A semiconductor chip is mounted on the first side. Plural metal anchor structures are coupled to the package substrate and project away from the first side. A molding layer is on the package substrate and at least partially encapsulates the semiconductor chip and the anchor structures. The anchor structures terminate in the molding layer and anchor the molding layer to the package substrate.

公开(公告)号：US11837588B2

公开(公告)日：2023-12-05

申请号：US17978389

申请日：2022-11-01

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Milind S. Bhagavat ,  Rahul Agarwal

IPC: H01L25/16 ,  H01L21/56 ,  H01L23/498 ,  H05K1/02 ,  H05K3/30 ,  H05K3/34 ,  H05K3/28

CPC classification number: H01L25/16 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/49838 ,  H05K1/0231 ,  H05K3/284 ,  H05K3/303 ,  H05K3/3442 ,  H05K2201/10015 ,  H05K2201/10522 ,  H05K2201/10636

Abstract: Various circuit boards with mounted passive components and method of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes at least partially encapsulating a first plurality of passive components in a molding material to create a first molded passive component group. The first molded passive component group is mounted on a surface of a circuit board. The first plurality of passive components are electrically connected to the circuit board.

公开(公告)号：US11804479B2

公开(公告)日：2023-10-31

申请号：US16586309

申请日：2019-09-27

Applicant: Advanced Micro Devices, Inc.

Inventor： John J. Wuu ,  Milind S. Bhagavat ,  Brett P. Wilkerson ,  Rahul Agarwal

IPC: H01L25/18 ,  H01L23/48 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L25/18 ,  H01L23/481 ,  H01L23/528 ,  H01L24/05 ,  H01L24/08 ,  H01L2224/0557 ,  H01L2224/08146

Abstract: Systems, apparatuses, and methods for routing traffic through vertically stacked semiconductor dies are disclosed. A first semiconductor die has a second die stacked vertically on top of it in a three-dimensional integrated circuit. The first die includes a through silicon via (TSV) interconnect that does not traverse the first die. The first die includes one or more metal layers above the TSV, which connect to a bonding pad interface through a bonding pad via. If the signals transferred through the TSV of the first die are shared by the second die, then the second die includes a TSV aligned with the bonding pad interface of the first die. If these signals are not shared by the second die, then the second die includes an insulated portion of a wafer backside aligned with the bonding pad interface.

公开(公告)号：US11742301B2

公开(公告)日：2023-08-29

申请号：US16544021

申请日：2019-08-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Rahul Agarwal ,  Milind S. Bhagavat ,  Priyal Shah ,  Chia-Hao Cheng ,  Brett P. Wilkerson ,  Lei Fu

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/214 ,  H01L2924/3511 ,  H01L2924/35121

Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package is provided that includes a fan-out redistribution layer (RDL) structure that has plural stacked polymer layers, plural metallization layers, plural conductive vias interconnecting adjacent metallization layers of the metallization layers, and plural rivets configured to resist delamination of one or more of the polymer layers. Each of the plural rivets includes a first head, a second head and a shank connected between the first head and the second head. The first head is part of one of the metallization layers. The shank includes at least one of the conductive vias and at least one part of another of the metallization layers.

公开(公告)号：US11437359B2

公开(公告)日：2022-09-06

申请号：US16799243

申请日：2020-02-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Brett P. Wilkerson ,  Milind S. Bhagavat ,  Rahul Agarwal ,  Dmitri Yudanov

IPC: H01L25/18 ,  H01L23/367 ,  H01L23/00 ,  H01L25/00 ,  H01L23/48

Abstract: A method for manufacturing a three-dimensional integrated circuit includes attaching a first side of a first die to a first carrier wafer. The method includes preparing a second side of the first die to generate a prepared second side of the first die. The method includes attaching the prepared second side of the first die to a second carrier wafer. The method includes removing the first carrier wafer from the first side of the first die to form a transitional three-dimensional integrated circuit. The method includes attaching a third carrier wafer to a first side of the transitional three-dimensional integrated circuit. The method includes attaching a first side of the second die to a second side of the transitional three-dimensional integrated circuit.

公开(公告)号：US10937755B2

公开(公告)日：2021-03-02

申请号：US16023399

申请日：2018-06-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Priyal Shah ,  Milind S. Bhagavat

IPC: H01L23/00

Abstract: Various chip stacks and methods and structures of interconnecting the same are disclosed. In one aspect, an apparatus is provided that includes a first semiconductor chip that has a first glass layer and plural first groups of plural conductor pads in the first glass layer. Each of the plural first groups of conductor pads is configured to bumplessly connect to a corresponding second group of plural conductor pads of a second semiconductor chip to make up a first interconnect of a plurality interconnects that connect the first semiconductor chip to the second semiconductor chip. The first glass layer is configured to bond to a second glass layer of the second semiconductor chip.

公开(公告)号：US10903168B2

公开(公告)日：2021-01-26

申请号：US16887184

申请日：2020-05-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Milind S. Bhagavat ,  Lei Fu ,  Farshad Ghahghahi

IPC: H01L23/538 ,  H01L25/16 ,  H01L23/31 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L21/683 ,  H01L23/00

Abstract: Various arrangements of multi-RDL structure devices are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer structure and a second redistribution layer structure mounted on the first redistribution layer structure. A first semiconductor chip is mounted on the second redistribution layer structure and electrically connected to both the second redistribution layer structure and the first redistribution layer structure.

公开(公告)号：US20200343236A1

公开(公告)日：2020-10-29

申请号：US16927111

申请日：2020-07-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Milind S. Bhagavat ,  Rahul Agarwal ,  Gabriel H. Loh

IPC: H01L25/18 ,  H01L23/538 ,  H01L23/498 ,  H01L25/00 ,  H01L23/433

Abstract: Various semiconductor chip devices and methods of manufacturing the same are disclosed. In one aspect, a semiconductor chip device is provided that has a reconstituted semiconductor chip package that includes an interposer that has a first side and a second and opposite side and a metallization stack on the first side, a first semiconductor chip on the metallization stack and at least partially encased by a dielectric layer on the metallization stack, and plural semiconductor chips positioned over and at least partially laterally overlapping the first semiconductor chip.

公开(公告)号：US20190393123A1

公开(公告)日：2019-12-26

申请号：US16563077

申请日：2019-09-06

Applicant: Advanced Micro Devices, Inc.

Inventor： John Wuu ,  Samuel Naffziger ,  Patrick J. Shyvers ,  Milind S. Bhagavat ,  Kaushik Mysore ,  Brett P. Wilkerson

IPC: H01L23/367 ,  H01L25/00 ,  H01L25/065

Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.