公开(公告)号：US08426278B2

公开(公告)日：2013-04-23

申请号：US12797420

申请日：2010-06-09

Applicant: Akif Sultan ,  Indradeep Sen

Inventor： Akif Sultan ,  Indradeep Sen

IPC: H01L21/00

CPC classification number: H01L27/088 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66636 ,  H01L29/7848

Abstract: Apparatus for semiconductor device structures and related fabrication methods are provided. A method for fabricating a semiconductor device structure on an isolated region of semiconductor material comprises forming a plurality of gate structures overlying the isolated region of semiconductor material and masking edge portions of the isolated region of semiconductor material. While the edge portions are masked, the fabrication method continues by forming recesses between gate structures of the plurality of gate structures and forming stressor regions in the recesses. The method continues by unmasking the edge portions and implanting ions of a conductivity-determining impurity type into the stressor regions and the edge portions.

Abstract translation: 提供了半导体器件结构和相关制造方法的装置。 在半导体材料的隔离区域上制造半导体器件结构的方法包括形成覆盖半导体材料的隔离区域和掩蔽半导体材料的隔离区域的边缘部分的多个栅极结构。 当边缘部分被掩蔽时，制造方法通过在多个栅极结构的栅极结构之间形成凹槽并在凹部中形成应力区域来继续。 该方法继续通过揭开边缘部分并将导电性确定杂质类型的离子注入到应力区域和边缘部分中。

公开(公告)号：US08377781B2

公开(公告)日：2013-02-19

申请号：US13230083

申请日：2011-09-12

Applicant: Jian Chen ,  James F. Buller ,  Akif Sultan

Inventor： Jian Chen ,  James F. Buller ,  Akif Sultan

IPC: H01L21/336

CPC classification number: H01L29/78618 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/7848

Abstract: The present invention is directed to a transistor with an asymmetric silicon germanium source region, and various methods of making same. In one illustrative embodiment, the transistor includes a gate electrode formed above a semiconducting substrate comprised of silicon, a doped source region comprising a region of epitaxially grown silicon that is doped with germanium formed in the semiconducting substrate and a doped drain region formed in the semiconducting substrate.

Abstract translation: 本发明涉及具有不对称硅锗源区的晶体管及其制造方法。 在一个说明性实施例中，晶体管包括形成在由硅构成的半导体衬底之上的栅电极，掺杂源区包括在半导体衬底中形成的锗掺杂的外延生长硅的区域和形成在半导体衬底中的掺杂漏极区 基质。

公开(公告)号：US07761838B2

公开(公告)日：2010-07-20

申请号：US11861492

申请日：2007-09-26

Applicant: Zhonghai Shi ,  Mark Michael ,  Donna Michael, legal representative ,  David Wu ,  James F. Buller ,  Jingrong Zhou ,  Akif Sultan

Inventor： Zhonghai Shi ,  Mark Michael ,  David Wu ,  James F. Buller ,  Jingrong Zhou ,  Akif Sultan

IPC: G06F17/50 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L29/78 ,  H01L29/7843

Abstract: The techniques and technologies described herein relate to the automatic creation of photoresist masks for stress liners used with semiconductor based transistor devices. The stress liner masks are generated with automated design tools that leverage layout data corresponding to features, devices, and structures on the wafer. A resulting stress liner mask (and wafers fabricated using the stress liner mask) defines a stress liner coverage area that extends beyond the boundary of the transistor area and into a stress insensitive area of the wafer. The extended stress liner further enhances performance of the respective transistor by providing additional compressive/tensile stress.

Abstract translation: 本文所述的技术和技术涉及自动创建与半导体基晶体管器件一起使用的应力衬垫的光致抗蚀剂掩模。 应力衬垫掩模是利用自动设计工具生成的，其利用与晶片上的特征，器件和结构对应的布局数据。 产生的应力衬垫掩模（以及使用应力衬垫掩模制造的晶片）限定了延伸超出晶体管区域的边界并进入晶片的应力不敏感区域的应力衬垫覆盖区域。 延伸的应力衬垫通过提供额外的压缩/拉伸应力来进一步提高相应晶体管的性能。

公开(公告)号：US07638837B2

公开(公告)日：2009-12-29

申请号：US11861051

申请日：2007-09-25

Applicant: Akif Sultan ,  Mark Michael ,  Donna Michael, legal representative ,  David Wu

Inventor： Akif Sultan ,  Mark Michael ,  David Wu

IPC: H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7843

Abstract: A stress-enhanced semiconductor device is provided which includes a substrate having an inactive region and an active region, a first-type stress layer overlying at least a portion of the active region, and a second-type stress layer. The active region includes a first lateral edge which defines a first width of the active region, and a second lateral edge which defines a second width of the active region. The second-type stress layer is disposed adjacent the second lateral edge of the active region.

Abstract translation: 提供一种应力增强型半导体器件，其包括具有非活性区域和有源区域的衬底，覆盖有源区域的至少一部分的第一类型应力层和第二类型应力层。 有源区域包括限定有源区域的第一宽度的第一侧边缘和限定有源区域的第二宽度的第二侧边缘。 第二类应力层设置在活动区域​​的第二侧边缘附近。

公开(公告)号：US07582493B2

公开(公告)日：2009-09-01

申请号：US11538872

申请日：2006-10-05

Applicant: Akif Sultan ,  James F. Buller ,  David Donggang Wu

Inventor： Akif Sultan ,  James F. Buller ,  David Donggang Wu

IPC: H01L21/66

CPC classification number: H01L22/12 ,  H01L22/14

Abstract: A test structure includes first and second pluralities of transistors. The first plurality of transistors includes gate electrodes of a first length. The second plurality of transistors includes gate electrodes of a second length different than the first length. A channel area of the transistors in the first plurality is substantially equal to a channel area of the transistors in the second plurality. A method for using the test structure includes measuring a performance metric of the first and second pluralities of transistors. Variation in the performance metric associated with the first plurality of transistors is compared to variation in the performance metric associated with the second plurality of transistors to identify a random length variation component associated with the first plurality of transistors.

Abstract translation: 测试结构包括第一和第二多个晶体管。 第一多个晶体管包括第一长度的栅电极。 第二多个晶体管包括与第一长度不同的第二长度的栅电极。 第一多个晶体管的沟道面积基本上等于第二多个晶体管的沟道面积。 使用该测试结构的方法包括测量第一和第二多个晶体管的性能度量。 将与第一多个晶体管相关联的性能度量的变化与与第二多个晶体管相关联的性能度量的变化进行比较，以识别与第一多个晶体管相关联的随机长度变化分量。

公开(公告)号：US06979635B1

公开(公告)日：2005-12-27

申请号：US10759171

申请日：2004-01-20

Applicant: Akif Sultan ,  Qi Xiang ,  Bin Yu

Inventor： Akif Sultan ,  Qi Xiang ,  Bin Yu

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/6653 ,  H01L21/28035 ,  H01L21/28123 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/976

Abstract: Ultra narrow and thin polycrystalline silicon gate electrodes are formed by patterning a polysilicon gate precursor, reducing its width and height by selectively oxidizing its upper and side surfaces, and then removing the oxidized surfaces. Embodiments include patterning the polysilicon gate precursor with an oxide layer thereunder, ion implanting to form deep source/drain regions, forming a nitride layer on the substrate surface on each side of the polysilicon gate precursor, thermally oxidizing the upper and side surfaces of the polysilicon gate precursor thereby consuming silicon, and then removing the oxidized upper and side surfaces leaving a polysilicon gate electrode with a reduced width and a reduced height. Subsequent processing includes forming shallow source/drain extensions, forming dielectric sidewall spacers on the polysilicon gate electrode and then forming metal silicide layers on the upper surface of the polysilicon gate electrode and over the source/drain regions.

Abstract translation: 通过图案化多晶硅栅极前体，通过选择性地氧化其上表面和侧表面，然后去除氧化表面而减小其宽度和高度来形成超窄和多晶硅栅电极。 实施例包括用其下面的氧化物层图案化多晶硅栅极前体，离子注入以形成深源极/漏极区域，在多晶硅栅极前体的每一侧的衬底表面上形成氮化物层，热氧化多晶硅的上表面和侧表面 从而消耗硅，然后去除氧化的上表面和侧表面，留下具有减小的宽度和降低的高度的多晶硅栅电极。 随后的处理包括形成浅源极/漏极延伸部分，在多晶硅栅电极上形成电介质侧壁间隔物，然后在多晶硅栅极电极的上表面上以及在源极/漏极区域上形成金属硅化物层。

公开(公告)号：US06642536B1

公开(公告)日：2003-11-04

申请号：US10015802

申请日：2001-12-17

Applicant: Qi Xiang ,  Akif Sultan

Inventor： Qi Xiang ,  Akif Sultan

IPC: H01L2906

CPC classification number: H01L21/76264 ,  H01L21/76232 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78639 ,  H01L29/78654

Abstract: Silicon on insulator technology and strained silicon technology provide semiconductor devices with high performance capabilities. Shallow trench isolation technology provides smaller devices with increased reliability. Bulk silicon technology provides devices requiring deep ion implant capabilities and/or a high degree of thermal management. A semiconductor device including silicon on insulator regions, strained silicon layer, shallow trench isolation structures, and bulk silicon regions is provided on a single semiconductor substrate.

Abstract translation: 硅绝缘体技术和应变硅技术为半导体器件提供了高性能的能力。 浅沟槽隔离技术为更小的器件提供了更高的可靠性。 散装硅技术提供了需要深度离子注入能力和/或高度热管理的器件。 包括硅绝缘体区域，应变硅层，浅沟槽隔离结构和体硅区域的半导体器件设置在单个半导体衬底上。

公开(公告)号：US06475885B1

公开(公告)日：2002-11-05

申请号：US09896490

申请日：2001-06-29

Applicant: Akif Sultan

Inventor： Akif Sultan

IPC: H01L21425

CPC classification number: H01L29/66772 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/6659 ,  H01L29/78609

Abstract: Various methods of fabricating a source/drain structure are provided. In one aspect, a method of processing a semiconductor workpiece is provided that includes implanting a neutral ion species into the substrate at a sub-amorphizing dosage to provide a plurality of interstitials and forming a source/drain region in the substrate by implanting impurities of a first conductivity type proximate the plurality of interstitials. The plurality of interstitials retards diffusion of the impurities. Impurity diffusion is retarded, resulting in better activation and a more abrupt impurity profile.

Abstract translation: 提供了制造源极/漏极结构的各种方法。 在一个方面，提供了一种处理半导体工件的方法，其包括以亚非晶化剂量将中性离子物质注入衬底中以提供多个间隙，并通过植入杂质形成衬底中的源极/漏极区域 靠近多个间隙的第一导电类型。 多个间隙延迟杂质的扩散。 杂质扩散延迟，导致更好的活化和更突变的杂质分布。

公开(公告)号：US08779529B2

公开(公告)日：2014-07-15

申请号：US13692369

申请日：2012-12-03

Applicant: Indradeep Sen ,  Thorsten Kammler ,  Andreas Knorr ,  Akif Sultan

Inventor： Indradeep Sen ,  Thorsten Kammler ,  Andreas Knorr ,  Akif Sultan

IPC: H01L21/02

CPC classification number: H01L29/78 ,  H01L21/28097 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/66606

Abstract: A semiconductor device is formed with low resistivity self aligned silicide contacts with high-K/metal gates. Embodiments include postponing silicidation of a metal layer on source/drain regions in a silicon substrate until deposition of a high-K dielectric, thereby preserving the physical and morphological properties of the silicide film and improving device performance. An embodiment includes forming a replaceable gate electrode on a silicon-containing substrate, forming source/drain regions, forming a metal layer on the source/drain regions, forming an ILD over the metal layer on the substrate, removing the replaceable gate electrode, thereby forming a cavity, depositing a high-K dielectric layer in the cavity at a temperature sufficient to initiate a silicidation reaction between the metal layer and underlying silicon, and forming a metal gate electrode on the high-K dielectric layer.

Abstract translation: 半导体器件形成为具有高K /金属栅极的低电阻率自对准硅化物接触。 实施例包括在硅衬底的源极/漏极区域上延迟金属层的硅化物，直到沉积高K电介质，从而保持硅化物膜的物理和形态特性并提高器件性能。 一个实施例包括在含硅衬底上形成可替换的栅电极，形成源极/漏极区域，在源极/漏极区域上形成金属层，在衬底上的金属层上形成ILD，去除可更换的栅电极，由此 形成空腔，在足以在金属层和下层硅之间引发硅化反应的温度下在腔中沉积高K电介质层，以及在高K电介质层上形成金属栅电极。

公开(公告)号：US20120018816A1

公开(公告)日：2012-01-26

申请号：US12843350

申请日：2010-07-26

Applicant: Indradeep Sen ,  Thorsten Kammler ,  Andreas Knorr ,  Akif Sultan

Inventor： Indradeep Sen ,  Thorsten Kammler ,  Andreas Knorr ,  Akif Sultan

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/78 ,  H01L21/28097 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/66606

Abstract: A semiconductor device is formed with low resistivity self aligned silicide contacts with high-K/metal gates. Embodiments include postponing silicidation of a metal layer on source/drain regions in a silicon substrate until deposition of a high-K dielectric, thereby preserving the physical and morphological properties of the silicide film and improving device performance. An embodiment includes forming a replaceable gate electrode on a silicon-containing substrate, forming source/drain regions, forming a metal layer on the source/drain regions, forming an ILD over the metal layer on the substrate, removing the replaceable gate electrode, thereby forming a cavity, depositing a high-K dielectric layer in the cavity at a temperature sufficient to initiate a silicidation reaction between the metal layer and underlying silicon, and forming a metal gate electrode on the high-K dielectric layer.

Abstract translation: 半导体器件形成为具有高K /金属栅极的低电阻率自对准硅化物接触。 实施例包括在硅衬底的源极/漏极区域上延迟金属层的硅化物，直到沉积高K电介质，从而保持硅化物膜的物理和形态特性并提高器件性能。 一个实施例包括在含硅衬底上形成可替换的栅电极，形成源极/漏极区域，在源极/漏极区域上形成金属层，在衬底上的金属层上形成ILD，去除可更换的栅电极，由此 形成空腔，在足以在金属层和下层硅之间引发硅化反应的温度下在腔中沉积高K电介质层，以及在高K电介质层上形成金属栅电极。