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    Structure of semiconductor device with sinker contact region
    23.
    发明授权
    Structure of semiconductor device with sinker contact region 有权
    具有沉降片接触区域的半导体器件的结构

    公开(公告)号：US07164186B2

    公开(公告)日：2007-01-16

    申请号：US10939221

    申请日：2004-09-10

    申请人： Angelo Pinto ,  Jeffrey A. Babcock ,  Michael Schober ,  Scott G. Balster ,  Christoph Dirnecker

    发明人： Angelo Pinto ,  Jeffrey A. Babcock ,  Michael Schober ,  Scott G. Balster ,  Christoph Dirnecker

    IPC分类号： H01L29/70

    CPC分类号： H01L29/66272 ,  H01L29/41708

    摘要： A method for manufacturing a semiconductor device includes forming a buried layer of a semiconductor substrate. An active region is formed adjacent at least a portion of the buried layer. A first isolation structure is formed adjacent at least a portion of the buried layer. A second isolation structure is formed adjacent at least a portion of the active region. A base layer is formed adjacent at least a portion of the active region. A dielectric layer is formed adjacent at least a portion of the base layer, and then at least part of the dielectric layer is removed at an emitter contact location and at a sinker contact location. An emitter structure is formed at the emitter contact location. Forming the emitter structure includes etching the semiconductor device at the sinker contact location to form a sinker contact region. The sinker contact region has a first depth. The method may also include forming a gate structure. Forming the gate structure includes etching the sinker contact region thereby increasing the first depth of the sinker contact region to a second depth.

    摘要翻译： 半导体器件的制造方法包括形成半导体衬底的掩埋层。 在掩埋层的至少一部分附近形成有源区。 在掩埋层的至少一部分附近形成第一隔离结构。 在活性区域的至少一部分附近形成第二隔离结构。 在活性区域的至少一部分附近形成基底层。 在基底层的至少一部分附近形成电介质层，然后在发射极接触位置和沉降片接触位置移除介电层的至少一部分。 发射极结构形成在发射极接触位置。 形成发射极结构包括在沉降片接触位置蚀刻半导体器件以形成沉降片接触区域。 沉降片接触区域具有第一深度。 该方法还可以包括形成栅极结构。 形成栅极结构包括蚀刻沉降片接触区域，从而将沉降片接触区域的第一深度增加到第二深度。

    Integrated process for high voltage and high performance silicon-on-insulator bipolar devices
    26.
    发明授权
    Integrated process for high voltage and high performance silicon-on-insulator bipolar devices 有权
    用于高电压和高性能绝缘体上的双极器件的集成工艺

    公开(公告)号：US06838348B2

    公开(公告)日：2005-01-04

    申请号：US10844144

    申请日：2004-05-12

    申请人： Jeffrey A. Babcock ,  Gregory E. Howard ,  Angelo Pinto ,  Phillipp Steinmann ,  Scott G. Balster

    发明人： Jeffrey A. Babcock ,  Gregory E. Howard ,  Angelo Pinto ,  Phillipp Steinmann ,  Scott G. Balster

    IPC分类号： H01L21/331 ,  H01L21/84 ,  H01L27/082 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/73

    CPC分类号： H01L29/66265 ,  H01L21/84 ,  H01L27/0826 ,  H01L27/1203 ,  H01L29/0692 ,  H01L29/0821 ,  H01L29/7317

    摘要： High-voltage bipolar transistors (30, 60) in silicon-on-insulator (SOI) integrated circuits are disclosed. In one disclosed embodiment, an collector region (28) is formed in epitaxial silicon (24, 25) disposed over a buried insulator layer (22). A base region (32) and emitter (36) are disposed over the collector region (28). Buried collector region (31) are disposed in the epitaxial silicon (24) away from the base region (32). The transistor may be arranged in a rectangular fashion, as conventional, or alternatively by forming an annular buried collector region (31). According to another disclosed embodiment, a high voltage transistor (60) includes a central isolation structure (62), so that the base region (65) and emitter region (66) are ring-shaped to provide improved performance. A process for fabricating the high voltage transistor (30, 60) simultaneously with a high performance transistor (40) is also disclosed.

    摘要翻译： 公开了绝缘体上硅（SOI）集成电路中的高电压双极晶体管（30,60）。 在一个公开的实施例中，集电极区域（28）形成在设置在掩埋绝缘体层（22）上的外延硅（24,25）中。 基极区域（32）和发射极（36）设置在集电极区域（28）的上方。 掩埋集电极区域（31）设置在远离基极区域（32）的外延硅（24）中。 晶体管可以以常规方式布置成矩形方式，或者通过形成环形埋层集电极区域（31）来布置。 根据另一公开的实施例，高压晶体管（60）包括中心隔离结构（62），使得基极区域（65）和发射极区域（66）是环形的，以提供改进的性能。 还公开了与高性能晶体管（40）同时制造高压晶体管（30,60）的工艺。

    Method and apparatus for the selective doping of semiconductor material by ion implantation
    28.
    发明授权
    Method and apparatus for the selective doping of semiconductor material by ion implantation 有权
    通过离子注入选择性掺杂半导体材料的方法和装置

    公开(公告)号：US06284615B1

    公开(公告)日：2001-09-04

    申请号：US09333691

    申请日：1999-06-16

    申请人： Angelo Pinto ,  Sergio Palara

    发明人： Angelo Pinto ,  Sergio Palara

    IPC分类号： H01L21265

    CPC分类号： H01L29/66287 ,  H01L21/2652 ,  H01L21/26586

    摘要： The method comprises forming an implantation screening layer of predetermined thickness on the wafer, forming, in the screening layer, a first rectilinear, elongate opening having a first width, and at least a second rectilinear, elongate opening substantially parallel to the first opening and having a second width smaller than the first width is formed on the screening layer. The wafer is then subjected to ion implantation with two ion beams directed in directions substantially perpendicular to the longitudinal axes of the openings and inclined to the surface of the wafer at predetermined angles so as to strike the openings from two opposite sides. The thickness of the screening layer, the widths of the openings, and the angles of inclination of the ion beams being selected in a manner such that the beams strike the base of the first opening for substantially uniform doping of the underlying area of the wafer, but do not strike the base of the second opening. The novel method and apparatus enables selective doping by ion implantation to be performed without the use of a mask which is otherwise necessary for screening the second opening.

    摘要翻译： 该方法包括在晶片上形成预定厚度的植入屏蔽层，在屏蔽层中形成具有第一宽度的第一直线细长开口和基本上平行于第一开口的至少第二直线细长开口，并且具有 在屏蔽层上形成小于第一宽度的第二宽度。 然后对晶片进行离子注入，其中两个离子束以基本上垂直于开口的纵向轴线的方向指向，并且以预定角度倾斜到晶片的表面，以便从两个相对的侧面冲击开口。 屏蔽层的厚度，开口的宽度和离子束的倾斜角度以使得光束撞击第一开口的基部以使晶片的下面区域基本均匀掺杂的方式被选择， 但不要打开第二个开口的基地。 新颖的方法和装置能够通过离子注入进行选择性掺杂，而不需要使用否则掩模第二开口所必需的掩模。

    Reduction of STI corner defects during SPE in semiconductor device fabrication using DSB substrate and hot technology
    29.
    发明授权
    Reduction of STI corner defects during SPE in semiconductor device fabrication using DSB substrate and hot technology 有权
    使用DSB基板和热技术在半导体器件制造过程中减少SPE中的角部缺陷

    公开(公告)号：US08846487B2

    公开(公告)日：2014-09-30

    申请号：US13544519

    申请日：2012-07-09

    申请人： Angelo Pinto ,  Periannan R. Chidambaram ,  Rick L. Wise

    发明人： Angelo Pinto ,  Periannan R. Chidambaram ,  Rick L. Wise

    IPC分类号： H01L21/76 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/762 ,  H01L29/04

    CPC分类号： H01L21/76275 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045

    摘要： A device and method of reducing residual STI corner defects in a hybrid orientation transistor comprising, forming a direct silicon bonded substrate wherein a second silicon layer with a second crystal orientation is bonded to a handle substrate with a first crystal orientation, forming a pad oxide layer on the second silicon layer, forming a nitride layer on the pad oxide layer, forming an isolation trench within the direct silicon bonded substrate through the second silicon layer and into the handle substrate, patterning a PMOS region of the direct silicon bonded substrate utilizing photoresist including a portion of the isolation trench, implanting and amorphizing an NMOS region of the direct silicon bonded substrate, removing the photoresist, performing solid phase epitaxy, performing a recrystallization anneal, forming an STI liner, completing front end processing, and performing back end processing.

    摘要翻译： 一种降低混合取向晶体管中的残留STI拐角缺陷的装置和方法，包括：形成直接硅键合衬底，其中具有第二晶体取向的第二硅层以第一晶体取向结合到手柄衬底上，形成衬垫氧化物层 在所述第二硅层上，在所述焊盘氧化物层上形成氮化物层，通过所述第二硅层在所述直接硅键合衬底内形成隔离沟槽并进入所述处理衬底，使用光致抗蚀剂构图所述直接硅键合衬底的PMOS区域 隔离沟槽的一部分，将直接硅键合衬底的NMOS区域注入和非晶化，去除光致抗蚀剂，进行固相外延，进行再结晶退火，形成STI衬垫，完成前端处理和执行后端处理。