公开(公告)号：US20080265289A1

公开(公告)日：2008-10-30

申请号：US11796985

申请日：2007-04-30

申请人： Anup Bhalla ,  Francios Hebert ,  Sung-Shan Tai ,  Sik K. Lui

发明人： Anup Bhalla ,  Francios Hebert ,  Sung-Shan Tai ,  Sik K. Lui

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/812 ,  H01L21/338

CPC分类号： H01L29/7813 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811

摘要： This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.

摘要翻译： 本发明公开了一种半导体功率器件。 沟槽半导体功率器件包括从半导体衬底的顶表面开口的沟槽栅极，被包围在设置在衬底底表面上的漏区以上的顶表面附近的体区中的源极区围绕。 所述半导体功率器件还包括植入离子块，所述植入离子块设置在所述身体区域旁边的台面区域的上表面上，所述植入离子块具有基本上大于0.3微米的厚度，用于阻挡体注入离子和源离子进入台面区域 从而可以减少用于制造半导体功率器件的掩模。

公开(公告)号：US20080090357A1

公开(公告)日：2008-04-17

申请号：US11983769

申请日：2007-11-09

申请人： Sung-Shan Tai ,  Tiesheng Li ,  Anup Bhalla ,  Hong Chang ,  Moses Ho

发明人： Sung-Shan Tai ,  Tiesheng Li ,  Anup Bhalla ,  Hong Chang ,  Moses Ho

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate, through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate structure that extends substantially above the top substrate surface.

摘要翻译： 一种制造半导体器件的方法包括在具有顶部衬底表面的衬底上形成硬掩模，在衬底中形成通过硬掩模的沟槽，在沟槽中沉积栅极材料，其中沉积在沟槽中的栅极材料的量 延伸超过顶部衬底表面，并且去除硬掩模以留下基本上在顶部衬底表面上方延伸的栅极结构。

公开(公告)号：US20070075360A1

公开(公告)日：2007-04-05

申请号：US11240255

申请日：2005-09-30

申请人： Hong Chang ,  Tiesheng Li ,  Sung-Shan Tai ,  Daniel Ng ,  Anup Bhalla

发明人： Hong Chang ,  Tiesheng Li ,  Sung-Shan Tai ,  Daniel Ng ,  Anup Bhalla

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/4941 ,  H01L29/66734 ,  H01L29/7811

摘要： This invention discloses an improved trenched metal oxide semiconductor field effect transistor (MOSFET) cell that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The MOSFET cell further includes a source contact opening opened on top of an area extended over the body region and the source region through a protective insulation layer wherein the area further has a cobalt-silicide layer disposed near a top surface of the substrate. The MOSFET cell further includes a Ti/TiN conductive layer covering the area interfacing with the cobalt-silicide layer over the source contact opening. The MOSFET cell further includes a source contact metal layer formed on top of the Ti/TiN conductive layer ready to form source-bonding wires thereon.

摘要翻译： 本发明公开了一种改进的沟槽金属氧化物半导体场效应晶体管（MOSFET）单元，其包括被包围在设置在基板的底表面上的漏极区域上方的体区域中的源极区域包围的沟槽栅极。 MOSFET单元进一步包括源极接触开口，该开口位于通过保护绝缘层延伸到主体区域上的区域的顶部，并且源区域通过保护绝缘层开放，其中该区域还具有设置在基板顶表面附近的硅化钴层。 MOSFET单元还包括覆盖源极接触开口上与硅化钴层接合的区域的Ti / TiN导电层。 MOSFET单元还包括形成在Ti / TiN导电层的顶部上的源极接触金属层，准备在其上形成源极接合线。

公开(公告)号：US20130126966A1

公开(公告)日：2013-05-23

申请号：US13747265

申请日：2013-01-22

申请人： Sik Lui ,  Anup Bhalla ,  Sik Lui

发明人： Sik Lui ,  Anup Bhalla

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7813 ,  H01L21/3081 ,  H01L21/31 ,  H01L21/32133 ,  H01L21/76224 ,  H01L27/088 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7827

摘要： An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. The device can be made using a three-mask or four-mask process.

摘要翻译： 氧化物终端半导体器件可以包括多个栅极沟槽，栅极流道和绝缘体端接沟槽。 栅极沟槽位于有源区域中。 每个栅极沟槽包括导电栅电极。 绝缘体端接沟槽位于围绕有源区域的端接区域中。 绝缘体端接沟槽填充有绝缘体材料以形成用于半导体器件的绝缘子端子。 该装置可以使用三掩模或四掩模工艺制成。

公开(公告)号：US09685523B2

公开(公告)日：2017-06-20

申请号：US14573187

申请日：2014-12-17

申请人： Madhur Bobde ,  Harsh Naik ,  Lingpeng Guan ,  Anup Bhalla ,  Sik Lui

发明人： Madhur Bobde ,  Harsh Naik ,  Lingpeng Guan ,  Anup Bhalla ,  Sik Lui

IPC分类号： H01L29/868 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/739

CPC分类号： H01L29/868 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/36 ,  H01L29/402 ,  H01L29/407 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7803 ,  H01L29/7839 ,  H01L29/861 ,  H01L29/8613 ,  H01L29/8725

摘要： This invention discloses a semiconductor device disposed in a semiconductor substrate. The semiconductor device includes a first semiconductor layer of a first conductivity type on a first major surface. The semiconductor device further includes a second semiconductor layer of a second conductivity type on a second major surface opposite the first major surface. The semiconductor device further includes an injection efficiency controlling buffer layer of a first conductivity type disposed immediately below the second semiconductor layer to control the injection efficiency of the second semiconductor layer.

公开(公告)号：US20120329225A1

公开(公告)日：2012-12-27

申请号：US13604286

申请日：2012-09-05

申请人： Anup Bhalla ,  Sik Lui ,  Tiesheng Li

发明人： Anup Bhalla ,  Sik Lui ,  Tiesheng Li

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811

摘要： Fabricating a semiconductor device includes forming a mask on a substrate having a top substrate surface; forming a gate trench in the substrate, through the mask; depositing gate material in the gate trench; removing the mask to leave a gate structure; implanting a body region; implanting a source region; forming a source body contact trench having a trench wall and a trench bottom; forming a plug in the source body contact trench, wherein the plug extends below a bottom of the body region; and disposing conductive material in the source body contact trench, on top of the plug.

摘要翻译： 制造半导体器件包括在具有顶部衬底表面的衬底上形成掩模; 通过掩模在衬底中形成栅极沟槽; 在栅极沟槽中沉积栅极材料; 取下面罩离开门结构; 植入人体区域; 植入源区; 形成具有沟槽壁和沟槽底部的源体接触沟槽; 在源体接触沟槽中形成插塞，其中插头延伸到身体区域的底部下方; 并且在所述源体接触沟槽中，在所述插头的顶部上设置导电材料。

公开(公告)号：US20110233666A1

公开(公告)日：2011-09-29

申请号：US12731112

申请日：2010-03-24

申请人： Sik Lui ,  Anup Bhalla

发明人： Sik Lui ,  Anup Bhalla

IPC分类号： H01L27/105 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/3081 ,  H01L21/31 ,  H01L21/32133 ,  H01L21/76224 ,  H01L27/088 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7827

摘要： An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. The device can be made using a three-mask or four-mask process.

摘要翻译： 氧化物终端半导体器件可以包括多个栅极沟槽，栅极流道和绝缘体端接沟槽。 栅极沟槽位于有源区域中。 每个栅极沟槽包括导电栅电极。 绝缘体端接沟槽位于围绕有源区域的端接区域中。 绝缘体端接沟槽填充有绝缘体材料以形成用于半导体器件的绝缘子端子。 该装置可以使用三掩模或四掩模工艺制成。

公开(公告)号：US20110042742A1

公开(公告)日：2011-02-24

申请号：US12917378

申请日：2010-11-01

申请人： Anup Bhalla ,  Dorman Pitzer ,  Jacek Korec ,  Xiaorong Shi ,  Sik Lui

发明人： Anup Bhalla ,  Dorman Pitzer ,  Jacek Korec ,  Xiaorong Shi ,  Sik Lui

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0661 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/8725 ,  H01L2924/0002 ,  Y10S257/905 ,  H01L2924/00

摘要： In a trench-gated MIS device contact is made to the gate within the trench, thereby eliminating the need to have the gate material, typically polysilicon, extend outside of the trench. This avoids the problem of stress at the upper corners of the trench. Contact between the gate metal and the polysilicon is normally made in a gate metal region that is outside the active region of the device. Various configurations for making the contact between the gate metal and the polysilicon are described, including embodiments wherein the trench is widened in the area of contact. Since the polysilicon is etched back below the top surface of the silicon throughout the device, there is normally no need for a polysilicon mask, thereby saving fabrication costs.

摘要翻译： 在沟槽栅极MIS器件中，沟槽内的栅极接触，从而不需要使栅极材料（通常为多晶硅）延伸到沟槽外部。 这避免了沟槽上角处的应力问题。 栅极金属和多晶硅之间的接触通常在位于器件的有源区域之外的栅极金属区域中形成。 描述了用于形成栅极金属和多晶硅之间的接触的各种构造，包括其中沟槽在接触区域中变宽的实施例。 由于在整个器件中多晶硅被回蚀到硅的顶表面之下，通常不需要多晶硅掩模，从而节省制造成本。

公开(公告)号：US20090224316A1

公开(公告)日：2009-09-10

申请号：US12384172

申请日：2009-03-31

申请人： Anup Bhalla ,  Sik Lui ,  Tiesheng Li

发明人： Anup Bhalla ,  Sik Lui ,  Tiesheng Li

IPC分类号： H01L29/772

CPC分类号： H01L29/7813 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811

摘要： A semiconductor device includes a drain, a body disposed over the drain, a source embedded in the body, a gate trench extending through the source and the body into the drain, a gate disposed in the gate trench, a source body contact trench extending through the source into the body, a conductive contact layer disposed along at least a portion of a source body contact trench sidewall and in contact with at least a portion of the source, and a trench filling material disposed in the source body contact trench and overlaying at least a portion of the conductive contact layer.

摘要翻译： 半导体器件包括漏极，设置在漏极上的主体，嵌入在主体中的源极，通过源极和主体延伸到漏极中的栅极沟槽，设置在栅极沟槽中的栅极，源体接触沟槽延伸穿过 源体进入体内，导电接触层沿着源体接触沟槽侧壁的至少一部分设置并与源的至少一部分接触，以及沟槽填充材料，其设置在源体接触沟槽中并覆盖在 至少一部分导电接触层。

公开(公告)号：US20070182435A1

公开(公告)日：2007-08-09

申请号：US11300082

申请日：2005-12-14

申请人： Sik Lui ,  Anup Bhalla

发明人： Sik Lui ,  Anup Bhalla

IPC分类号： G01R31/26

CPC分类号： G01R31/2621 ,  G01R31/2831 ,  G01R31/327

摘要： This invention discloses a circuit for performing an unclamped inductive test on a metal oxide semiconductor field effect transistor (MOSFET) device driven by a gate driver. The circuit includes a current sense circuit for measuring an unclamped inductive testing (UIS) current that increases with an increase of a pulse width inputted from the gate driver to the MOSFET device wherein the current sensing circuit is provided to turn off the gate driver when a predefined UIS current is reached. The test circuit further includes a MOSFET failure detection circuit connected to a drain terminal of the MOSFET device for measuring a drain voltage change for detecting the MOSFET failure during the UIS test. The test circuit further includes a first switch for switching ON/OFF a power supply to the MOSFET device to and a second switch connected between a drain and source terminal of the MOSFET. Furthermore, the test circuit further includes a timing and make before break (MBB) circuit for receiving an MOSFET failure signal from the MOSFET failure detection circuit and for controlling the first and second switches for switching off a power supply to the MOSFET device upon a detection of an UIS failure under the UIS test to prevent damages to a probe

摘要翻译： 本发明公开了一种用于对由栅极驱动器驱动的金属氧化物半导体场效应晶体管（MOSFET）器件执行未钳位电感测试的电路。 该电路包括电流检测电路，用于测量从栅极驱动器输入到MOSFET器件的脉冲宽度增加而增加的未钳位电感测试（UIS）电流，其中提供电流检测电路以在栅极驱动器 达到预定义的UIS电流。 测试电路还包括连接到MOSFET器件的漏极端子的MOSFET故障检测电路，用于测量在UIS测试期间检测MOSFET故障的漏极电压变化。 测试电路还包括用于将MOSFET器件的电源接通/断开的第一开关和连接在MOSFET的漏极和源极端子之间的第二开关。 此外，测试电路还包括用于从MOSFET故障检测电路接收MOSFET故障信号的定时和断开前（MBB）电路，并且用于在检测时控制用于关断到MOSFET器件的电源的第一和第二开关 在统计研究所测试下的统计研究所失败，以防止探针受损