公开(公告)号：US20160098965A1

公开(公告)日：2016-04-07

申请号：US14504215

申请日：2014-10-01

Applicant: Apple Inc.

Inventor： Hao-Lin Chiu ,  Byung Duk Yang ,  Chun-Yao Huang ,  Kyung Wook Kim ,  Shih Chang Chang ,  Szu-Hsien Lee

IPC: G09G3/36 ,  G02F1/1362 ,  H01L23/528 ,  G02F1/1368 ,  H01L27/12 ,  H01L23/522

CPC classification number: G09G3/3648 ,  G02F1/13338 ,  G02F1/134309 ,  G02F1/1345 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/13456 ,  G06F3/0412 ,  G06F3/0416 ,  G06F3/044 ,  G06F2203/04103 ,  G06F2203/04104 ,  G06F2203/04112 ,  G09F9/30 ,  G09G3/3666 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0413 ,  G09G2300/0426 ,  G09G2310/0281 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/124 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A display may have an array of pixels arranged in rows and columns. Each pixel may have a transistor for controlling the amount of output light associated with that pixel. The transistors may be thin-film transistors having active areas, first and second source-drain terminals, and gates. Gate lines may be used to distribute gate control signals to the gates of the transistors in each row. Data lines that run perpendicular to the gate lines may be used to distribute image data along columns of pixels. The gate lines may be connected to gate line extensions that run parallel to the data lines. The data lines may each overlap a respective one of the gate line extensions. Vias may be used to connect the gate line extensions to the gate lines. The gate line extensions may all have the same length.

Abstract translation: 显示器可以具有排列成行和列的像素阵列。 每个像素可以具有用于控制与该像素相关联的输出光量的晶体管。 晶体管可以是具有有源区的薄膜晶体管，第一和第二源极 - 漏极端子和栅极。 栅极线可用于将栅极控制信号分配到每行中的晶体管的栅极。 垂直于栅极线延伸的数据线可用于沿像素列分布图像数据。 栅极线可以连接到平行于数据线延伸的栅极线扩展。 数据线可以各自重叠相应的一个栅极线延伸。 通孔可用于将栅极线延伸部分连接到栅极线。 门线扩展可能都具有相同的长度。

公开(公告)号：US20140370655A1

公开(公告)日：2014-12-18

申请号：US14474433

申请日：2014-09-02

Applicant: Apple Inc.

Inventor： Ming-Chin Hung ,  Kyung Wook Kim ,  Young Bae Park ,  Hao-Lin Chiu ,  Chun-Yao Huang ,  Shih Chang Chang

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/66742 ,  H01L27/1225 ,  H01L29/42364 ,  H01L29/42384 ,  H01L29/786 ,  H01L29/7869

Abstract: A method is provided for fabricating a thin-film transistor (TFT). The method includes forming a semiconductor layer over a gate insulator that covers a gate electrode, and depositing an insulator layer over the semiconductor layer, as well as etching the insulator layer to form a patterned etch-stop without losing the gate insulator. The method also includes forming a source electrode and a drain electrode over the semiconductor layer and the patterned etch-stop. The method further includes removing a portion of the semiconductor layer beyond the source electrode and the drain electrode such that a remaining portion of the semiconductor layer covers the gate insulator in a first overlapping area of the source electrode and the gate electrode and a second overlapping area of the drain electrode and gate electrode.

公开(公告)号：US12211435B2

公开(公告)日：2025-01-28

申请号：US18470216

申请日：2023-09-19

Applicant: Apple Inc.

Inventor： Sun-Il Chang ,  Kwang Soon Park ,  Hao-Lin Chiu ,  Jie Won Ryu ,  Hyunsoo Kim ,  Hyunwoo Nho ,  Wei Xiong ,  Patrick R Cruce

IPC: G09G5/10 ,  G01R31/28 ,  G09G3/3208

Abstract: An electronic device may include an electronic display having a gate-on-array (GOA) that generates gate signals in response to an activation signal, pixels that activate in response to a combination of the gate signals and data signals indicative of image data, and sensing circuitry. The sensing circuitry may measure a characteristic response of a gate signal a characteristic response of one or more pixels, or both and compare the characteristic responses to baselines. The electronic device may also include compensation circuitry that applies a compensation to the activation signal and/or to the image data based on the comparisons between the characteristic responses and the baselines.

公开(公告)号：US20240169903A1

公开(公告)日：2024-05-23

申请号：US18470216

申请日：2023-09-19

Applicant: Apple Inc.

Inventor： Sun-Il Chang ,  Kwang Soon Park ,  Hao-Lin Chiu ,  Jie Won Ryu ,  Hyunsoo Kim ,  Hyunwoo Nho ,  Wei Xiong ,  Patrick R. Cruce

IPC: G09G3/3208

CPC classification number: G09G3/3208 ,  G09G2300/0408 ,  G09G2300/0413 ,  G09G2310/0289 ,  G09G2320/045

Abstract: An electronic device may include an electronic display having a gate-on-array (GOA) that generates gate signals in response to an activation signal, pixels that activate in response to a combination of the gate signals and data signals indicative of image data, and sensing circuitry. The sensing circuitry may measure a characteristic response of a gate signal a characteristic response of one or more pixels, or both and compare the characteristic responses to baselines. The electronic device may also include compensation circuitry that applies a compensation to the activation signal and/or to the image data based on the comparisons between the characteristic responses and the baselines.

公开(公告)号：US11966544B2

公开(公告)日：2024-04-23

申请号：US18323659

申请日：2023-05-25

Applicant: Apple Inc.

Inventor： Shinya Ono ,  Suhwan Moon ,  Dong-Gwang Ha ,  Jiaxi Hu ,  Hao-Lin Chiu ,  Kwang Soon Park ,  Hassan Edrees ,  Wen-I Hsieh ,  Jiun-Jye Chang ,  Chin-Wei Lin ,  Kyung Wook Kim

IPC: G06F3/041 ,  G06F3/044 ,  G09G3/3208

CPC classification number: G06F3/04184 ,  G06F3/0412 ,  G06F3/0444 ,  G06F3/0446 ,  G09G3/3208 ,  G06F2203/04107 ,  G06F2203/04112

Abstract: An electronic device may have a display with touch sensors. One or more shielding layers may be interposed between the display and the touch sensors. The display may include transistors with gate conductors, a first planarization layer formed over the gate conductors, one or more contacts formed in a first source-drain layer within the first planarization layer, a second planarization layer formed on the first planarization layer, one or more data lines formed in a second source-drain layer within the second planarization layer, a third planarization layer formed on the second planarization layer, and a data line shielding structure formed at least partly in a third source-drain layer within the third planarization layer. The data line shielding structure may be a routing line, a blanket layer, a mesh layer formed in one or more metal layers, and/or a data line covering another data line.

公开(公告)号：US20220059018A1

公开(公告)日：2022-02-24

申请号：US17406012

申请日：2021-08-18

Applicant: Apple Inc.

Inventor： Shatam Agarwal ,  Sean C. Chang ,  Hao-Lin Chiu ,  Fenghua Zheng ,  Pierre-Yves Emelie ,  Yao Chen ,  Marc Albrecht ,  Mingxia Gu ,  Jun Qi ,  Wei Chen

IPC: G09G3/32

Abstract: A light emitting diode (LED) display can calculate a common voltage charge of a line of pixels in the LED display, the common voltage charge comprising a difference between a first line of pixels and a second line of pixels. If the calculated common voltage charge exceeds a predetermined threshold, a toggle matrix can be generated for the line of pixels. The toggle matrix can include a matrix of charge values generated by calculating a difference in charge values for each subpixel a first line of subpixels with each subpixel a second line of subpixels. The LED display can identify one or more regions of subpixels exhibiting the predetermined toggle pattern in the toggle matrix. The LED display can generate a voltage correction charge to apply to affected regions of the display. Alternatively, the subpixels or pixels could be swapped with adjacent pixels to reduce toggling or settling error.

公开(公告)号：US11087710B2

公开(公告)日：2021-08-10

申请号：US16147045

申请日：2018-09-28

Applicant: Apple Inc.

Inventor： Pei-Yu Hou ,  Yang Li ,  Hao-Lin Chiu

IPC: G09G3/36 ,  G09G3/3225

Abstract: A display includes a plurality of pixels grouped into a plurality of lines of pixels. Each line of pixels of the plurality of lines comprises a group of pixels of the plurality of pixels that are coupled to a common scan line as well and that are coupled to different data lines to individually activate each pixel of the group of pixels. The display also includes a common voltage (VCOM) driving circuit configured to receive a waveform and drive the waveform to the display as a VCOM having a value tailored to an individually activated pixel of the group of pixels.

公开(公告)号：US10210830B2

公开(公告)日：2019-02-19

申请号：US15631410

申请日：2017-06-23

Applicant: Apple Inc.

Inventor： Byung Duk Yang ,  Szu-Hsien Lee ,  Kyung-Wook Kim ,  Shih Chang Chang ,  Chun-Yao Huang ,  Hao-Lin Chiu

IPC: G09G3/36 ,  G02F1/1368 ,  G02F1/1362 ,  H01L23/528 ,  H01L23/522 ,  H01L27/12 ,  G02F1/1345 ,  G06F3/041 ,  G06F3/044 ,  G09F9/30 ,  G02F1/1333 ,  G02F1/1343

Abstract: A display may have an array of pixels arranged in rows and columns. Each pixel may have a transistor for controlling the amount of output light associated with that pixel. The transistors may be thin-film transistors having active areas, first and second source-drain terminals, and gates. Gate lines may be used to distribute gate control signals to the gates of the transistors in each row. Data lines that run perpendicular to the gate lines may be used to distribute image data along columns of pixels. The gate lines may be connected to gate line extensions that run parallel to the data lines. The data lines may each overlap a respective one of the gate line extensions. Vias may be used to connect the gate line extensions to the gate lines. The gate line extensions may all have the same length.

公开(公告)号：US10170072B2

公开(公告)日：2019-01-01

申请号：US14860397

申请日：2015-09-21

Applicant: APPLE INC.

Inventor： Byung Duk Yang ,  Chun-Yao Huang ,  Kyung Wook Kim ,  Patrick B. Bennett ,  Shih Chang Chang ,  Wonjae Choi ,  Hao-Lin Chiu ,  Kwang Soon Park ,  Xinyu Zhu

IPC: G09G5/00 ,  G09G3/20 ,  G02F1/1345

Abstract: A display device may include pixels and source lines that provide data line signals to the pixels. The display device may also include gate lines that provide gate signals to switches associated with the pixels. The display device may also include vertical gate lines disposed generally parallel to the source lines and coupled to the gate lines at cross point nodes. The display device may also include compensation lines, such that each compensation line is proximate to a respective vertical gate line. The compensation lines may transmit compensation signals having an opposite polarity as compared to respective gate signals to reduce or eliminate a kickback voltage on at least one of the plurality of pixels.

公开(公告)号：US09606382B2

公开(公告)日：2017-03-28

申请号：US14712311

申请日：2015-05-14

Applicant: Apple Inc.

Inventor： Young-Jik Jo ,  Chun-Yao Huang ,  Hao-Lin Chiu ,  Kwang Soon Park ,  Shih Chang Chang

IPC: G09G3/34 ,  G02F1/133 ,  G02F1/1343

CPC classification number: G02F1/13306 ,  G02F1/134336 ,  G09G3/3655

Abstract: A display has an array of pixels controlled by display driver circuitry. Gate driver circuitry supplies gate line signals to rows of the pixels. The pixels may be liquid crystal display pixels. Each pixel may have a common electrode voltage terminal. The display may have a transparent conductive film that forms a common electrode voltage layer that overlaps that array and that is shorted to the common electrode voltage terminals of the pixels. Metal common electrode voltage lines may run across the transparent conductive film to reduce resistance. Metal common electrode voltage paths that are coupled to the metal common electrode voltage lines may run along the left and right edge of the display. Common electrode voltage compensation circuits may receive feedback from the metal common electrode voltage paths. There may be two or more common electrode voltage compensation circuits for both the left and right edges of the display.