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    Generation of Tone Mapping Function for Dynamic Pixel and Backlight Control
    21.
    发明申请
    Generation of Tone Mapping Function for Dynamic Pixel and Backlight Control 审中-公开
    用于动态像素和背光控制的色调映射功能的生成

    公开(公告)号：US20140078193A1

    公开(公告)日：2014-03-20

    申请号：US14023420

    申请日：2013-09-10

    Applicant: APPLE INC.

    Inventor： Ulrich T. Barnhoefer ,  Robert E. Jeter

    IPC: G09G3/36

    CPC classification number: G09G5/10 ,  G09G3/3406 ,  G09G3/3607 ,  G09G2320/0271 ,  G09G2320/0626 ,  G09G2320/0646 ,  G09G2360/16

    Abstract: Systems, methods, and devices are provided for generating a tone mapping function used in adjusting the power consumed by a backlight of an electronic display. One such method includes sampling an image frame in framebuffer space and generating a tone mapping function in linear space. The tone mapping function may have at least two portions: a nondistorting portion that does not to distort pixels to which it applies when an intensity of a backlight of the electronic display is modified and a distorting portion that does distort pixels to which it applies when the intensity of the backlight is modified. Thereafter, the intensity of the backlight may be modified based at least in part on the nondistorting portion of the tone mapping function, the tone mapping function converted to framebuffer space, and the tone mapping function applied to the image frame or a subsequent image frame.

    Abstract translation: 提供了系统，方法和装置，用于产生用于调节电子显示器的背光消耗的功率的色调映射功能。 一种这样的方法包括对帧缓冲空间中的图像帧进行采样并在线性空间中产生色调映射函数。 色调映射功能可以具有至少两个部分：当电子显示器的背光的强度被修改时，不会使其应用的像素失真的非失真部分，以及当该 改变背光的强度。 此后，可以至少部分地基于色调映射功能的非安排部分，转换为帧缓冲器空间的色调映射功能和应用于图像帧或后续图像帧的色调映射功能来修改背光的强度。

    Histogram Generation and Evaluation for Dynamic Pixel and Backlight Control
    22.
    发明申请
    Histogram Generation and Evaluation for Dynamic Pixel and Backlight Control 有权
    动态像素和背光控制的直方图生成和评估

    公开(公告)号：US20140078166A1

    公开(公告)日：2014-03-20

    申请号：US14023412

    申请日：2013-09-10

    Applicant: APPLE INC.

    Inventor： Ulrich T. Barnhoefer ,  Robert E. Jeter

    IPC: G09G5/10

    CPC classification number: G09G5/10 ,  G09G3/3406 ,  G09G3/3607 ,  G09G2320/0271 ,  G09G2320/0626 ,  G09G2320/0646 ,  G09G2360/16

    Abstract: Systems, methods, and devices are provided for histogram generation and evaluation used in adjusting the power consumed by a backlight of an electronic display. One such method involves generating a pixel brightness histogram of an image frame passing through a pixel pipeline in a nonlinear space. One or more pixel brightness values from the histogram may be selected before being converted from the nonlinear space into a linear space. A tone mapping function and backlight intensity are determined based at least in part on the one or more pixel brightness values in the linear space. The resulting tone mapping function is converted to the nonlinear space and applied to the image frame or a subsequent image frame in the pixel pipeline. The pixels of the image frame to which the nondistorting portion of the tone mapping function is applied may appear substantially undistorted despite a reduction in backlight intensity.

    Abstract translation: 提供了系统，方法和设备用于调整电子显示器的背光消耗的功率的直方图生成和评估。 一种这样的方法涉及生成通过非线性空间中的像素流水线的图像帧的像素亮度直方图。 在从非线性空间转换成线性空间之前，可以选择来自直方图的一个或多个像素亮度值。 至少部分地基于线性空间中的一个或多个像素亮度值来确定色调映射功能和背光强度。 所得到的色调映射函数被转换为非线性空间，并应用于像素管线中的图像帧或后续图像帧。 即使应用了色调映射功能的非失真部分的图像帧的像素也可能基本上不失真，尽管背光强度降低。

    Voltage Ramp Memory Calibration
    23.
    发明申请
    Voltage Ramp Memory Calibration 有权

    公开(公告)号：US20250104790A1

    公开(公告)日：2025-03-27

    申请号：US18525088

    申请日：2023-11-30

    Applicant: Apple Inc.

    Inventor： Robert E. Jeter ,  Jingkui Zheng ,  Srinivasa Rao Masanam

    IPC: G11C29/12 ,  G11C29/46

    Abstract: An apparatus for performing memory calibrations during a performance state change is disclosed. A memory controller is configured to convey a clock signal to a memory and includes a calibration control circuit configured to perform a plurality of calibrations of the clock signal during a change from a first one to a second one of a plurality of performance states, and a delay circuit configured to apply a delay to clock signal conveyed to the memory. In performing a one of the calibrations, the calibration control circuit is configured to convey, to the memory, a first command to begin a timing test that generates a count value indicative of a current voltage of the memory, receive the count value from the memory at a conclusion of the timing test, and cause the delay circuit to adjust, based on the count value, the delay applied to the clock signal.

    Memory Subsystem Calibration Using Substitute Results
    24.
    发明公开
    Memory Subsystem Calibration Using Substitute Results 审中-公开

    公开(公告)号：US20240062792A1

    公开(公告)日：2024-02-22

    申请号：US18455385

    申请日：2023-08-24

    Applicant: Apple Inc.

    Inventor： Robert E. Jeter ,  Rakesh L. Notani ,  Kai Lun Hsiung ,  Venkata Ramana Malladi ,  Rahul Ranjan ,  Naveen Kumar Korada

    IPC: G11C7/22 ,  G06F11/10 ,  G11C7/10

    CPC classification number: G11C7/22 ,  G06F11/1076 ,  G11C7/10 ,  G11C2207/2254

    Abstract: A memory subsystem and method for performing calibrations therein is disclosed. A memory subsystem includes a memory controller coupled to a memory by a plurality of signal paths. The memory controller is configured to perform an initial calibration to determine respective eye patterns corresponding to the ones of the plurality of signal paths. For a subsequent calibration, updated eye patterns are determined for a subset of the plurality of signal paths. Remaining ones of the plurality of signal paths (not included in the subset), are not active during the subsequent calibrations. Updated eye patterns for the remaining ones of the plurality of signal paths are determined based on information obtained during the initial calibration and information from signal paths in the subset designated proxies for the remaining ones of the plurality of signal paths.

    Memory subsystem calibration using substitute results
    25.
    发明授权
    Memory subsystem calibration using substitute results 有权

    公开(公告)号：US11776597B2

    公开(公告)日：2023-10-03

    申请号：US17646741

    申请日：2022-01-03

    Applicant: Apple Inc.

    Inventor： Robert E. Jeter ,  Rakesh L. Notani ,  Kai Lun Hsiung ,  Venkata Ramana Malladi ,  Rahul Ranjan ,  Naveen Kumar Korada

    IPC: G11C7/22 ,  G06F11/10 ,  G11C7/10

    CPC classification number: G11C7/22 ,  G06F11/1076 ,  G11C7/10 ,  G11C2207/2254

    Abstract: A memory subsystem and method for performing calibrations therein is disclosed. A memory subsystem includes a memory controller coupled to a memory by a plurality of signal paths. The memory controller is configured to perform an initial calibration to determine respective eye patterns corresponding to the ones of the plurality of signal paths. For a subsequent calibrations, updated eye patterns are determined for a subset of the plurality of signal paths. Remaining ones of the plurality of signal paths (not included in the subset), are not active during the subsequent calibrations. Updated eye patterns for the remaining ones of the plurality of signal paths are determined based on information obtained during the initial calibration and information from signal paths in the subset designated proxies for the remaining ones of the plurality of signal paths.

    Duty cycle correction with read and write calibration
    26.
    发明授权
    Duty cycle correction with read and write calibration 有权

    公开(公告)号：US10734983B1

    公开(公告)日：2020-08-04

    申请号：US16277263

    申请日：2019-02-15

    Applicant: Apple Inc.

    Inventor： Robert E. Jeter ,  Rakesh L. Notani ,  Kai Lun Hsiung ,  Yanzhe Liu

    IPC: G11C11/409 ,  H03K3/017 ,  H03K5/156

    Abstract: A method and apparatus for performing duty cycle correction with read/write calibrations is disclosed. A first calibration is performed in a memory subsystem having a memory and a memory controller. The first calibration includes conveying a first clock signal from the memory controller to the memory, and determining the duty cycle of the first clock signal. If the duty cycle is not within a specified range, the duty cycle is adjusted and the process repeated. After the duty cycle of the first clock signal is within the specified range, a second calibration is performed, the second calibration including conveying a second clock signal from the memory to the memory controller. The duty cycle of the first clock signal may be further adjusted based on the second calibration.

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