-
21.发明授权公开(公告)号：US09294103B2
公开(公告)日：2016-03-22
申请号：US14180976
申请日：2014-02-14
Applicant: Apple Inc.
Inventor： Jong-Suk Lee , Shih-Chieh R. Wen , Toshinari Takayanagi , Wei-Han Lien
CPC classification number: H03L7/08 , G06F1/08 , G06F1/3237 , G06F1/324 , H03K5/00006 , H03L7/10 , H03L2207/10 , Y02D10/126 , Y02D10/128 , Y02D50/20
Abstract: A method and apparatus for achieving fast PLL lock when exiting a low power state is disclosed. In one embodiment, a method includes operating a PLL in a first state in which the PLL is locked to a first frequency. The method further includes programming the PLL to operate in a second state in which the PLL is locked to a second frequency. The programming may occur while the PLL is operating in the first state, and the PLL may continue operating in the first state after programming is complete. Thereafter, the PLL may be transitioned from the first state to a low power state. Upon exiting the low power state, the PLL may transition directly to the second state, locking to the second frequency, without having to transition to the first state or lock to the first frequency.
Abstract translation: 公开了一种在退出低功率状态时实现快速PLL锁定的方法和装置。 在一个实施例中，一种方法包括在PLL锁定到第一频率的第一状态下操作PLL。 该方法还包括对PLL进行编程以在PLL被锁定到第二频率的第二状态下工作。 当PLL处于第一状态时，可能会发生编程，并且编程完成后，PLL可能继续在第一状态下工作。 此后，PLL可以从第一状态转换到低功率状态。 在退出低功率状态时，PLL可以直接转换到第二状态，锁定到第二频率，而不必转换到第一状态或锁定到第一频率。
-
公开(公告)号：US20140215182A1
公开(公告)日：2014-07-31
申请号：US13750013
申请日：2013-01-25
Applicant: APPLE INC.
Inventor： Josh P. de Cesare , Gerard R. Williams, III , Michael J. Smith , Wei-Han Lien
IPC: G06F9/30
CPC classification number: G06F9/322 , G06F9/30076
Abstract: In an embodiment, an integrated circuit includes at least one processor. The processor may include a reset vector base address register configured to store a reset vector address for the processor. Responsive to a reset, the processor may be configured to capture a reset vector address on an input, updating the reset vector base address register. Upon release from reset, the processor may initiate instruction execution at the reset vector address. The integrated circuit may further include a logic circuit that is coupled to provide the reset vector address. The logic circuit may include a register that is programmable with the reset vector address. More particularly, in an embodiment, the register may be programmable via a write operation issued by the processor (e.g. a memory-mapped write operation). Accordingly, the reset vector address may be programmable in the integrated circuit, and may be changed from time to time.
Abstract translation: 在一个实施例中，集成电路包括至少一个处理器。 处理器可以包括被配置为存储处理器的复位向量地址的复位向量基地址寄存器。 响应于复位，处理器可以被配置为捕获输入上的复位向量地址，更新复位向量基地址寄存器。 当复位释放时，处理器可以在复位向量地址处启动指令执行。 集成电路还可以包括耦合以提供复位向量地址的逻辑电路。 逻辑电路可以包括可用复位向量地址编程的寄存器。 更具体地，在一个实施例中，寄存器可以通过由处理器发出的写入操作来编程（例如，存储器映射的写入操作）。 因此，复位矢量地址可以在集成电路中可编程，并且可以不时地改变。
-
公开(公告)号：US12236244B1
公开(公告)日：2025-02-25
申请号：US17810253
申请日：2022-06-30
Applicant: Apple Inc.
Inventor： Wei-Han Lien , Muawya M. Al-Otoom , Ian D. Kountanis , Niket K. Choudhary , Pruthivi Vuyyuru
IPC: G06F9/38
Abstract: A multi-degree branch predictor is disclosed. A processing circuit includes an instruction fetch circuit configured to fetch branch instructions, and a branch prediction circuit having a plurality of prediction subcircuits. The prediction subcircuits are configured to store different amounts of branch history data with respect to other ones, and to receive an indication of a given branch instruction in a particular clock cycle. The prediction subcircuits implement a common branch prediction scheme to output, in different clock cycles, corresponding predictions for the given branch instruction using the different amounts of branch history data and cause, instruction fetches to be performed by the instruction fetch circuit. The prediction subcircuits are also configured to override, in subsequent clock cycles, instruction fetches caused by prediction subcircuits with comparatively less branch history data based on contrary predictions performed in subsequent clock cycles by prediction subcircuits with more branch history data.
-
公开(公告)号：US20240385842A1
公开(公告)日：2024-11-21
申请号：US18774678
申请日：2024-07-16
Applicant: Apple Inc.
Inventor： Ian D Kountanis , Douglas C Holman , Wei-Han Lien , Pruthivi Vuyyuru , Ethan R Schuchman , Niket K Choudhary , Kulin N Kothari , Haoyan Jia
IPC: G06F9/38
Abstract: A processor may include a bias prediction circuit and an instruction prediction circuit to provide respective predictions for a conditional instruction. The bias prediction circuit may provide a bias prediction whether a condition of the conditional instruction is biased true or biased false. The instruction prediction circuit may provide an instruction prediction whether the condition of the conditional instruction is true of false. Responsive to a bias prediction that the condition of the conditional instruction is biased true or biased false, the processor may use the bias prediction from the bias prediction circuit to speculatively process the conditional instruction. Otherwise, the processor may use the instruction prediction from the instruction prediction circuit to speculatively process the conditional instruction.
-
公开(公告)号：US20230244495A1
公开(公告)日：2023-08-03
申请号：US17590722
申请日：2022-02-01
Applicant: Apple Inc.
Inventor： Ethan R. Schuchman , Niket K. Choudhary , Kulin N. Kothari , Haoyan Jia , Ian D. Kountanis , Douglas C. Holman , Wei-Han Lien , Pruthivi Vuyyuru
CPC classification number: G06F9/3844 , G06F9/3861 , G06F9/30145 , G06F9/30058 , G06F9/30079
Abstract: A processor may include an instruction distribution circuit and a plurality of execution pipelines. The instruction distribution circuit may distribute a conditional instruction to a first execution pipeline for execution when the conditional instruction is associated with a prediction of a high confidence level, or to a second execution pipeline for execution when the conditional instruction is associated with a prediction of a low confidence level. The second execution pipeline, not the first execution pipeline, may directly instruct the processor to obtain an instruction from a target address for execution, when the conditional instruction is mispredicted. Thus, when the conditional instruction is distributed to the first execution pipeline for execution and determined to be mispredicted, the first execution pipeline may cause the conditional instruction to be re-executed in the second execution pipeline to cause the instruction from the correct target address to be obtained for execution.
-
Patent Agency Ranking
公开(公告)号：US20190235601A1
公开(公告)日：2019-08-01
申请号：US16379231
申请日：2019-04-09
Applicant: Apple Inc.
Inventor： Jong-Suk Lee , Daniel C. Murray , Wei-Han Lien
IPC: G06F1/3206 , G06F1/3287 , G06F1/3296 , G06F1/324 , G06F9/50
CPC classification number: G06F1/3206 , G06F1/3203 , G06F1/3215 , G06F1/3228 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/5094 , Y02D10/126 , Y02D10/171 , Y02D10/172 , Y02D10/22
Abstract: In an embodiment, a system may include multiple processors and an automatic power state controller (APSC) configured to switch the processors between various operating points. The operating points may be described by data programmed into the APSC, and the APSC may include a register that is programmable with a target operating point request identifying a target operating point for the processors from among the described operating points. The data describing the operating points may also include an indication of whether or not the number of processors that may be concurrently active at the operating point is limited. Based on the indication and the number of active processors, the APSC may override the requested operating point with a reduced operating point. In some embodiments, a digital power estimator (DPE) may monitor operation of the processors and may throttle the processors when high power consumption is detected.
-
公开(公告)号：US10303238B2
公开(公告)日：2019-05-28
申请号：US15609915
申请日：2017-05-31
Applicant: Apple Inc.
Inventor： Jong-Suk Lee , Daniel C. Murray , Wei-Han Lien
IPC: G06F1/32 , G06F1/3206 , G06F1/324 , G06F1/3287 , G06F9/50 , G06F1/3296 , G06F1/3203 , G06F1/3228 , G06F1/3215
Abstract: In an embodiment, a system may include multiple processors and an automatic power state controller (APSC) configured to switch the processors between various operating points. The operating points may be described by data programmed into the APSC, and the APSC may include a register that is programmable with a target operating point request identifying a target operating point for the processors from among the described operating points. The data describing the operating points may also include an indication of whether or not the number of processors that may be concurrently active at the operating point is limited. Based on the indication and the number of active processors, the APSC may override the requested operating point with a reduced operating point. In some embodiments, a digital power estimator (DPE) may monitor operation of the processors and may throttle the processors when high power consumption is detected.
-
公开(公告)号：US09959120B2
公开(公告)日：2018-05-01
申请号：US13750013
申请日：2013-01-25
Applicant: Apple Inc.
Inventor： Josh P. de Cesare , Gerard R. Williams, III , Michael J. Smith , Wei-Han Lien
CPC classification number: G06F9/322 , G06F9/30076
Abstract: In an embodiment, an integrated circuit includes at least one processor. The processor may include a reset vector base address register configured to store a reset vector address for the processor. Responsive to a reset, the processor may be configured to capture a reset vector address on an input, updating the reset vector base address register. Upon release from reset, the processor may initiate instruction execution at the reset vector address. The integrated circuit may further include a logic circuit that is coupled to provide the reset vector address. The logic circuit may include a register that is programmable with the reset vector address. More particularly, in an embodiment, the register may be programmable via a write operation issued by the processor (e.g. a memory-mapped write operation). Accordingly, the reset vector address may be programmable in the integrated circuit, and may be changed from time to time.
-
公开(公告)号：US20170262036A1
公开(公告)日：2017-09-14
申请号：US15609915
申请日：2017-05-31
Applicant: Apple Inc.
Inventor： Jong-Suk Lee , Daniel C. Murray , Wei-Han Lien
CPC classification number: G06F1/3206 , G06F1/3203 , G06F1/3228 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/5094 , Y02D10/126 , Y02D10/171 , Y02D10/172 , Y02D10/22
Abstract: In an embodiment, a system may include multiple processors and an automatic power state controller (APSC) configured to switch the processors between various operating points. The operating points may be described by data programmed into the APSC, and the APSC may include a register that is programmable with a target operating point request identifying a target operating point for the processors from among the described operating points. The data describing the operating points may also include an indication of whether or not the number of processors that may be concurrently active at the operating point is limited. Based on the indication and the number of active processors, the APSC may override the requested operating point with a reduced operating point. In some embodiments, a digital power estimator (DPE) may monitor operation of the processors and may throttle the processors when high power consumption is detected.
-
公开(公告)号：US09541984B2
公开(公告)日：2017-01-10
申请号：US13910584
申请日：2013-06-05
Applicant: Apple Inc.
Inventor： Shih-Chieh R. Wen , Jason M. Kassoff , Wei-Han Lien
CPC classification number: G06F1/3228 , G06F1/3206 , G06F1/3275 , G06F1/3278 , Y02D10/14 , Y02D10/157
Abstract: A system and a method which include one or more processors, a memory coupled to at least one of the processors, a communication link coupled to the memory, and a power management unit. The power management unit may be configured to detect an inactive state of at least one of the processors. The power management unit may be configured to disable the communication link at a time after the processor enters the inactive state, and disable the memory at another time after the processor enters the inactive state.
Abstract translation: 包括一个或多个处理器，耦合到至少一个处理器的存储器，耦合到存储器的通信链路和电源管理单元的系统和方法。 电源管理单元可以被配置为检测至少一个处理器的不活动状态。 电源管理单元可以被配置为在处理器进入非活动状态之后的一个时间禁用通信链路，并且在处理器进入非活动状态之后的另一时间禁用该存储器。
-
-
-
-
-
-
-
-
-
Search Results
34
records
(took 0.025 seconds)
