公开(公告)号：US20200020389A1

公开(公告)日：2020-01-16

申请号：US16036751

申请日：2018-07-16

Applicant: Arm Limited

Inventor： Mudit Bhargava

IPC: G11C11/419

Abstract: Various implementations described herein refer to an integrated circuit having a bitcell coupled to a bitline. The integrated circuit may include a write driver coupled to the bitline for writing data to the bitcell. The write driver may have an inverter and a clamping device that are arranged to clamp current after data has been written to the bitcell.

公开(公告)号：US10270416B2

公开(公告)日：2019-04-23

申请号：US15410922

申请日：2017-01-20

Applicant: ARM Limited

Inventor： Bal S. Sandhu ,  Mudit Bhargava ,  Akshay Kumar ,  Piyush Agarwal ,  Shidhartha Das

IPC: H03H7/06 ,  H03H7/065 ,  H03H7/01 ,  H01L27/10 ,  H01L45/00

Abstract: Many kinds of filters are found in electronic circuits and provide a range of signal processing applications. Such filters can be passive, active, analog or digital and work across a range of frequencies. Present techniques provide an electronic filter circuit comprising resistive and capacitive elements, wherein a resistive element of the filter circuit is provided by a correlated electron material device.

公开(公告)号：US20160253227A1

公开(公告)日：2016-09-01

申请号：US14633062

申请日：2015-02-26

Applicant: ARM Limited

Inventor： Andy Wangkun Chen ,  Mudit Bhargava ,  Paul Meyer ,  Vikas Chandra

IPC: G06F11/07 ,  G06F11/08 ,  G06F11/10

CPC classification number: G06F11/076 ,  G06F11/085 ,  G06F11/1012 ,  G06F11/1016

Abstract: Various implementations described herein may refer to and may be directed to error detection circuitry for use with memory. In one implementation, an integrated circuit may include a memory array having a plurality of rows of memory cells, where a respective row is configured to store a data word and one or more check bits corresponding to the data word. The integrated circuit may also include inline error detection circuitry coupled to the respective row and configured to generate one or more flag bit values based on a detection of one or more bit errors in the data word stored in the respective row. The integrated circuit may further include error correction circuitry configured to correct the one or more bit errors in the data word stored in the respective row in response to the one or more generated flag bit values.

Abstract translation: 本文描述的各种实现可以指代并且可以涉及用于与存储器一起使用的错误检测电路。 在一个实现中，集成电路可以包括具有多行存储器单元的存储器阵列，其中相应的行被配置为存储对应于数据字的数据字和一个或多个校验位。 集成电路还可以包括耦合到相应行并且被配置为基于检测存储在相应行中的数据字中的一个或多个位错误来生成一个或多个标志位值的在线错误检测电路。 集成电路还可以包括错误校正电路，其配置为响应于一个或多个生成的标志位值来校正存储在相应行中的数据字中的一个或多个位错误。

公开(公告)号：US12080378B2

公开(公告)日：2024-09-03

申请号：US17709076

申请日：2022-03-30

Applicant: Arm Limited

Inventor： Fernando García Redondo ,  Pranay Prabhat ,  Mudit Bhargava ,  Supreet Jeloka

IPC: G11C7/12 ,  G11C5/12 ,  G11C7/16 ,  G11C7/18 ,  G11C8/08

CPC classification number: G11C7/12 ,  G11C5/12 ,  G11C7/16 ,  G11C7/18 ,  G11C8/08

Abstract: According to one implementation of the present disclosure, a circuit comprises: a memory array comprising one or more groupings of bitcells, one or more bitlines, and one or more wordlines; and one or more canary circuits coupled to the memory array, wherein each of the canary circuits is configured to predict at least partial breakdown of a corresponding grouping of bitcells in the memory array. According to one implementation of the present disclosure, a method includes: providing an excitation stress on one or more canary circuits corresponding to a grouping of bitcells in a memory array; detecting at least a partial breakdown of the one or more canary circuits; and generating a flag.

公开(公告)号：US20230317126A1

公开(公告)日：2023-10-05

申请号：US17709076

申请日：2022-03-30

Applicant: Arm Limited

Inventor： Fernando García Redondo ,  Pranay Prabhat ,  Mudit Bhargava ,  Supreet Jeloka

IPC: G11C7/12 ,  G11C7/18 ,  G11C7/16 ,  G11C8/08 ,  G11C5/12

CPC classification number: G11C7/12 ,  G11C7/18 ,  G11C7/16 ,  G11C8/08 ,  G11C5/12

Abstract: According to one implementation of the present disclosure, a circuit comprises: a memory array comprising one or more groupings of bitcells, one or more bitlines, and one or more wordlines; and one or more canary circuits coupled to the memory array, wherein each of the canary circuits is configured to predict at least partial breakdown of a corresponding grouping of bitcells in the memory array. According to one implementation of the present disclosure, a method includes: providing an excitation stress on one or more canary circuits corresponding to a grouping of bitcells in a memory array; detecting at least a partial breakdown of the one or more canary circuits; and generating a flag.

公开(公告)号：US20220343970A1

公开(公告)日：2022-10-27

申请号：US17238683

申请日：2021-04-23

Applicant: Arm Limited

Inventor： Rahul Mathur ,  Mudit Bhargava ,  Andy Wangkun Chen

IPC: G11C11/4093 ,  G11C11/408 ,  G11C11/4094 ,  G11C5/06

Abstract: Various implementations described herein are directed to a device having a multi-tiered memory structure with a first tier and a second tier arranged vertically in a stacked configuration. The device may have multiple transistors disposed in the multi-tiered memory structure with first transistors disposed in the first tier and second transistors disposed in the second tier. The device may have a single interconnect that vertically couples the first transistors in the first tier to the second transistors in the second tier.

公开(公告)号：US11437090B2

公开(公告)日：2022-09-06

申请号：US16036751

申请日：2018-07-16

Applicant: Arm Limited

Inventor： Mudit Bhargava

IPC: G11C11/419

Abstract: Various implementations described herein refer to an integrated circuit having a bitcell coupled to a bitline. The integrated circuit may include a write driver coupled to the bitline for writing data to the bitcell. The write driver may have an inverter and a clamping device that are arranged to clamp current after data has been written to the bitcell.

公开(公告)号：US20220164127A1

公开(公告)日：2022-05-26

申请号：US17103632

申请日：2020-11-24

Applicant: Arm Limited

Inventor： Mudit Bhargava ,  Paul Nicholas Whatmough ,  Supreet Jeloka ,  Zhi-Gang Liu

IPC: G06F3/06 ,  G06N3/063

Abstract: A memory for an artificial neural network (ANN) accelerator is provided. The memory includes a first bank, a second bank and a bank selector. Each bank includes at least two word lines and a plurality of write word selectors. Each word line stores a plurality of words, and each word has a plurality of bytes. Each write word selector has an input port and a plurality of output ports, is coupled to a corresponding word in each word line, and is configured to select a byte of the corresponding word of a selected word line based on a byte select signal. The bank selector is coupled to the write word selectors of the first bank and the second bank, and configured to select a combination of write word selectors from at least one of the first bank and the second bank based on a bank select signal.

公开(公告)号：US20210389520A1

公开(公告)日：2021-12-16

申请号：US17288498

申请日：2019-10-23

Applicant: Arm Limited

Inventor： Vinay Vashishtha ,  Mudit Bhargava ,  Brian Tracy Cline ,  Saurabh Pijuskumar Sinha ,  Gregory Munson Yeric

IPC: G02B6/12 ,  G02B6/26 ,  G02B6/42

Abstract: Disclosed are devices and techniques for facilitating transmission of light signals between optical waveguides formed on integrated circuit (IC) devices. In an implementation, one or more first waveguides may be formed in a structure such that at least a portion of the one or more first waveguides are exposed for optical connectivity. The structure may comprise first features to enable the structure to be interlocked with an IC device comprising second features complementary with the first features, so as to align at least a portion of the one or more first waveguides exposed to optically couple with one or more second waveguides formed in the first integrated circuit device.

公开(公告)号：US20210295915A1

公开(公告)日：2021-09-23

申请号：US17221670

申请日：2021-04-02

Applicant: Arm Limited

Inventor： Akhilesh Ramlaut Jaiswal ,  Mudit Bhargava

IPC: G11C14/00 ,  G11C11/16 ,  G11C11/418 ,  G11C11/419

Abstract: Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate transfer of stored values between the volatile and non-volatile memory bitcells.