公开(公告)号：US4584535A

公开(公告)日：1986-04-22

申请号：US622349

申请日：1984-06-19

申请人： Evert Seevinck

发明人： Evert Seevinck

IPC分类号： G05F3/26 ,  G05F3/22 ,  H03F3/45

CPC分类号： G05F3/227

摘要： In a current source circuit, a first and a second PNP transistor have commoned base electrodes, their emitters being connected through resistors to the positive supply voltage terminal. The collector lead of the first transistor includes a current source, which supplies a current which is reproduced at the output terminal. The commoned base electrodes are driven by a third transistor connected as an emitter follower, its emitter lead including a current source. The base of the third transistor is connected through a resistor to the positive supply voltage terminal as a result of which supply voltage variations appear also at the commoned bases of the first and second transistors so that the output current at the output terminal is substantially independent of supply voltage variations. A differential amplifier comprising fourth and fifth transistors, in which the base of the fourth transistor is connected to the collector of the first transistor and the base of the fifth transistor is connected to a reference voltage, controls the voltage at the base of the third transistor so that the collector current of the first transistor is substantially equal to the current of the current source.

摘要翻译： 在电流源电路中，第一和第二PNP晶体管具有共用的基极，其发射极通过电阻器连接到正电源电压端子。 第一晶体管的集电极引线包括电流源，其提供在输出端再现的电流。 普通基极由作为射极跟随器连接的第三晶体管驱动，其发射极引线包括电流源。 第三晶体管的基极通过电阻器连接到正电源电压端子，由此在第一和第二晶体管的共用基极处也出现电源电压变化，使得输出端子处的输出电流基本上独立于 电源电压变化。 一种包括第四和第五晶体管的差分放大器，其中第四晶体管的基极连接到第一晶体管的集电极，第五晶体管的基极连接到参考电压，控制第三晶体管的基极处的电压 使得第一晶体管的集电极电流基本上等于电流源的电流。

公开(公告)号：US6140664A

公开(公告)日：2000-10-31

申请号：US408088

申请日：1995-03-21

申请人： Evert Seevinck ,  Tjerk G. Spanjer

发明人： Evert Seevinck ,  Tjerk G. Spanjer

IPC分类号： H01J1/308 ,  H01J1/30 ,  H01J29/04 ,  H01J29/50 ,  H01L29/12

CPC分类号： H01J1/308 ,  H01J29/04 ,  H01J2201/319

摘要： To prevent breakdown of an insulating layer located underneath a gate electrode, the gate electrode is connected to an external terminal via a high-ohmic resistor. The high-ohmic resistor may form part of a resistive network for biasing voltages for a plurality of gate electrodes. The resistive network may be realised partly on the insulating layer.

摘要翻译： 为了防止位于栅电极下方的绝缘层的击穿，栅电极通过高欧姆电阻连接到外部端子。 高欧姆电阻可以形成用于多个栅电极的偏置电压的电阻网络的一部分。 电阻网络可以部分地实现在绝缘层上。

公开(公告)号：US5329481A

公开(公告)日：1994-07-12

申请号：US989629

申请日：1992-12-14

申请人： Evert Seevinck ,  Maarten Vertregt ,  Godefridus A. M. Hurkx

发明人： Evert Seevinck ,  Maarten Vertregt ,  Godefridus A. M. Hurkx

IPC分类号： H01L21/8247 ,  G11C11/34 ,  H01L21/8229 ,  H01L27/102 ,  H01L27/115

CPC分类号： G11C11/34

摘要： A semiconductor device with at least one programmable memory cell which includes a bipolar transistor (T.sub.1) with an emitter (11) and a collector (12) of a first conductivity type and a base (10) of a second, opposite conductivity type. The emitter (11) and collector (12) are coupled to a first supply line (100) and a second supply line (200), respectively. The base (10) is coupled to writing means (WRITE) through a control transistor (T.sub.2). Reading means (READ) are included in a current path (I) which extends between the first supply line (100) and the second supply line (200) and which includes a current path between the emitter (11) and collector (12). In a preferred embodiment, the collector (12) is in addition coupled to the second supply line (200) via a switchable load (T.sub.5).

摘要翻译： 一种具有至少一个可编程存储单元的半导体器件，其包括具有第一导电类型的发射极（11）和集电极（12）的双极晶体管（T1）和具有第二导电类型的第二基极（10）。 发射极（11）和集电极（12）分别耦合到第一电源线（100）和第二供电线（200）。 基极（10）通过控制晶体管（T2）耦合到写入装置（WRITE）。 读取装置（READ）包括在第一电源线（100）和第二电源线（200）之间延伸的电流路径（I）中，并且包括发射器（11）和集电极（12）之间的电流路径。 在优选实施例中，收集器（12）还经由可切换负载（T5）耦合到第二供电管线（200）。

公开(公告)号：US5173656A

公开(公告)日：1992-12-22

申请号：US690446

申请日：1991-04-23

申请人： Evert Seevinck ,  Philip D. Costello

发明人： Evert Seevinck ,  Philip D. Costello

IPC分类号： G05F3/26

CPC分类号： G05F3/262 ,  Y10S323/907

摘要： A reference generator includes a first, a second and an additional third current mirror for generating both a reference output current and a reference output voltage. As the reference output voltage only depends on the gate-source voltages of transistors which are fed with a constant current, the reference output voltage has a constant value and is substantially independent of the ambient temperature.

公开(公告)号：US5006815A

公开(公告)日：1991-04-09

申请号：US418414

申请日：1989-10-06

申请人： Eric A. M. Klumperink ,  Evert Seevinck

发明人： Eric A. M. Klumperink ,  Evert Seevinck

IPC分类号： H03F1/32 ,  H03F3/16 ,  H03G1/04 ,  H03G3/10

CPC分类号： H03F1/3211 ,  H03G1/04

摘要： A linear-gain amplifier arrangement comprises a current amplifying cell consisting of field-effect transistors and comprising a first (M1, M3) and a second (M2, M4current-mirror circuit whose respective input transistors (M1; M2) and output transistors (M3; M4) constitute a first and a second differential pair. The input transistors (M1; M2) have their drain electrodes connected to voltage-current converter (V/I) made up of field-effect transistors. The V/I converter supplies difference currents (I.sub.in1 ; I.sub.in2) which are square-law functions of the input voltage (U.sub.in) to be amplified. The difference between these input currents is a linear function of the input voltage. When the transistors are operated in their saturation regions the difference between the output currents (I.sub.out1 ; I.sub.out2) is also a linear function of the input voltage (U.sub.in). By adding a direct voltage (V.sub.c) to the gate-source voltage of the input and output transistors or by adding a direct current (I.sub.c) to the respective input currents (I.sub.in1 ; I.sub.in2) the gain can be varied without a change in bandwidth. When the arrangement is constructed as an integrated semiconductor circuit its gain can be made immune to temperature variations and tolerances in the fabrication process.

公开(公告)号：US4857861A

公开(公告)日：1989-08-15

申请号：US162921

申请日：1988-03-02

申请人： Evert Seevinck ,  Willem De Jager ,  Buitendijk

发明人： Evert Seevinck ,  Willem De Jager ,  Buitendijk

IPC分类号： H03F1/32 ,  H03F3/20 ,  H03F3/30 ,  H03F3/45

CPC分类号： H03F3/3093 ,  H03F1/3217 ,  H03F2203/30045

摘要： The first (T.sub.1) and the second (T.sub.2) output transistor of an amplifier arrangement are push-pull driven by means of a drive circuit (10) having two transistors (T.sub.11, T.sub.12) which are each loaded by a current source (T.sub.13, T.sub.14). Currents which are a measure of the currents flowing through the first (T.sub.1) and the second (T.sub.2) output transistor are generated by first (20) and second (30) current measuring means. These currents are applied to a control circuit (40) which controls the current intensity of the current sources (T.sub.13, T.sub.14) in such a way that the harmonic mean value of the currents flowing through the first (T.sub.1) and the second (T.sub.2) output transistor is substantially equal to a reference value.

公开(公告)号：US4853645A

公开(公告)日：1989-08-01

申请号：US249623

申请日：1988-09-26

申请人： Evert Seevinck ,  Willem De Jager ,  Pieter Buitendijk

发明人： Evert Seevinck ,  Willem De Jager ,  Pieter Buitendijk

IPC分类号： H03F1/32 ,  H03F3/20 ,  H03F3/30 ,  H03F3/45

CPC分类号： H03F3/3093 ,  H03F1/3217 ,  H03F2203/30045

摘要： The first (T.sub.1) and the second (T.sub.2) output transistor of an amplifier arrangement are push-pull driven by means of a drive circuit (10) having two transistors (T.sub.11, T.sub.12) which are each loaded by a current source (T.sub.13, T.sub.14). Currents which are a measure of the currents flowing through the first (T.sub.1) and the second (T.sub.2) output transistor are generated by first (20) and second (30) current measuring means. These currents are applied to a negative feedback means (40) which controls the current intensity of the current sources (T.sub.13, T.sub.14) in such a way that the harmonic mean value of the currents flowing through the first (T.sub.1) and the second (T.sub.2) output transistor is substantially equal to a reference value.

公开(公告)号：US07038936B2

公开(公告)日：2006-05-02

申请号：US10503459

申请日：2003-01-20

申请人： Evert Seevinck ,  Alain Michel Marie Thijs ,  Patrick Van De Steeg ,  Maurits Mario Nicolaas Storms

发明人： Evert Seevinck ,  Alain Michel Marie Thijs ,  Patrick Van De Steeg ,  Maurits Mario Nicolaas Storms

IPC分类号： G11C11/00

CPC分类号： G11C7/062 ,  G11C11/419

摘要： A reading circuit comprises a first and second cascode circuit and a first and second current mirror. The first cascode circuit can be connected to a bit line of a memory cell and the second cascode circuit can be connected to a reference bit line of a reference cell. The first output terminals of the first and second cascode circuits are connected to first terminals of the first and second current mirrors, respectively. The second output terminals of the first and second cascode circuits are connected to the second terminals of the second and first current mirrors, respectively. A tri-state buffer is coupled between the second terminals of the first and second current mirrors said buffer having bit invert capabilities.

摘要翻译： 读取电路包括第一和第二共源共栅电路以及第一和第二电流镜。 第一级联电路可以连接到存储器单元的位线，并且第二级联电路可以连接到参考单元的参考位线。 第一和第二共源共栅电路的第一输出端分别连接到第一和第二电流镜的第一端。 第一和第二共源共栅电路的第二输出端分别连接到第二和第一电流镜的第二端。 三态缓冲器耦合在第一和第二电流镜的第二端之间，所述缓冲器具有位反转能力。

公开(公告)号：US06489708B1

公开(公告)日：2002-12-03

申请号：US09218548

申请日：1998-12-22

申请人： Albertus A. S. Sluyterman ,  Evert Seevinck

发明人： Albertus A. S. Sluyterman ,  Evert Seevinck

IPC分类号： H01J3100

CPC分类号： H01J29/46 ,  H01J31/203 ,  H01J2229/0761 ,  H01J2231/1255

摘要： A cathode ray tube device in which two deflection yokes and two electron guns are used, but in which only one shadow mask is used. Image uniformity is obtained by creating a partial overlap of the two images created by the two yokes.

摘要翻译： 使用两个偏转轭和两个电子枪的阴极射线管装置，其中仅使用一个荫罩。 通过创建由两个轭创建的两个图像的部分重叠来获得图像均匀性。

公开(公告)号：US06205070B1

公开(公告)日：2001-03-20

申请号：US09464856

申请日：1999-12-16

申请人： Evert Seevinck ,  Lodewijk P. Bellefroid ,  Rene Segaar

发明人： Evert Seevinck ,  Lodewijk P. Bellefroid ,  Rene Segaar

IPC分类号： G11C700

CPC分类号： G11C11/419 ,  G11C7/062

摘要： A memory in an integrated circuit contains a current sense amplifier. The current sense amplifier contains a first and second input transistor with cross-coupled gates and drains, each transistor having a source coupled to a respective memory bit line. The current from the drains of the first and second input transistor is guided to source-drain channels of the first and second load transistor respectively. The drains of the first and second input transistor are coupled to a common node via source-gate links of the first and second load transistor respectively. The gate/source voltage drops of the first and second load transistor are arranged in a direction opposite to a direction of gate/source voltage drops of the first and second input transistor between the complementary bit lines and the common node.

摘要翻译： 集成电路中的存储器包含电流检测放大器。 电流检测放大器包含具有交叉耦合栅极和漏极的第一和第二输入晶体管，每个晶体管具有耦合到相应存储器位线的源极。 来自第一和第二输入晶体管的漏极的电流分别被引导到第一和第二负载晶体管的源极 - 漏极通道。 第一和第二输入晶体管的漏极分别通过第一和第二负载晶体管的源极 - 栅极耦合到公共节点。 第一和第二负载晶体管的栅极/源极电压降沿与互补位线和公共节点之间的第一和第二输入晶体管的栅极/源极电压降的方向相反的方向排列。