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    High write and erase efficiency embedded flash cell
    21.
    发明申请
    High write and erase efficiency embedded flash cell 有权
    高写入和擦除效率嵌入式闪存单元

    公开(公告)号：US20050282337A1

    公开(公告)日：2005-12-22

    申请号：US10870774

    申请日：2004-06-17

    Applicant: Der-Shin Shyu ,  Hung-Cheng Sung ,  Chen-Ming Huang

    Inventor： Der-Shin Shyu ,  Hung-Cheng Sung ,  Chen-Ming Huang

    IPC: H01L21/336 ,  H01L21/4763 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788

    CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

    Abstract: An embedded flash cell structure comprising a structure, a first floating gate having an exposed side wall over the structure, a second floating gate having an exposed side wall over the structure and spaced apart from the first floating gate, a first pair of spacers over the respective first floating gate and the second floating gate, a second pair of spacers at least over the respective exposed side walls of the first and second floating gates, a source area in the structure between the second pair of spacers, a plug over the source implant, and first and second control gates outboard of the first pair of spacers and exposing outboard portions of the structure and respective drain areas in the exposed outboard portions of the structure is provided. A method of forming the embedded flash cell structure is also provided.

    Abstract translation: 一种嵌入式闪存单元结构，其包括结构，第一浮动栅极，其具有在所述结构上方的暴露侧壁，第二浮动栅极，具有在所述结构上并与所述第一浮动栅极间隔开的暴露的侧壁; 相应的第一浮动栅极和第二浮动栅极，至少在第一和第二浮动栅极的相应暴露的侧壁上方的第二对间隔物，在第二对间隔物之间​​的结构中的源极区域，源极植入物 并且设置在第一对间隔件外侧的第一和第二控制门，并且暴露在结构的暴露的外侧部分中的结构的外侧部分和相应的漏极区域。 还提供了一种形成嵌入式闪存单元结构的方法。

    Method of reducing stress migration in integrated circuits
    22.
    发明授权
    Method of reducing stress migration in integrated circuits 有权
    减少集成电路应力迁移的方法

    公开(公告)号：US06855648B2

    公开(公告)日：2005-02-15

    申请号：US10601163

    申请日：2003-06-20

    Applicant: Chen-Ming Huang ,  Sen-Shan Yang

    Inventor： Chen-Ming Huang ,  Sen-Shan Yang

    IPC: H01L21/768 ,  H01L23/532 ,  H01L21/324

    CPC classification number: H01L21/76877 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method for reducing stress migration in the copper interconnect line is set forth. In accordance with the method, two anneal steps take place: The first step is at low temperature and of relatively short duration (e.g., about 25-300° C., and about 10 seconds-10 hours). After the first anneal, the wafer is cooled to room temperature. The second step is performed after the cooling step; a higher anneal temperature and longer time duration is needed to enhance performance.

    Abstract translation: 阐述了一种减少铜互连线中的应力迁移的方法。 根据该方法，发生两个退火步骤：第一步是在低温和相对短的持续时间（例如约25-300℃，约10秒-10小时）。 第一次退火后，将晶片冷却至室温。 第二步在冷却步骤之后进行; 需要更高的退火温度和更长的持续时间来增强性能。

    Architecture to suppress bit-line leakage
    23.
    发明授权
    Architecture to suppress bit-line leakage 有权
    抑制位线泄漏的体系结构

    公开(公告)号：US06819593B2

    公开(公告)日：2004-11-16

    申请号：US10318458

    申请日：2002-12-13

    Applicant: Der-Shin Shyu ,  Hung-Cheng Sung ,  Li-Wen Chang ,  Han-Ping Chen ,  Chen-Ming Huang ,  Ya-Chen Kao

    Inventor： Der-Shin Shyu ,  Hung-Cheng Sung ,  Li-Wen Chang ,  Han-Ping Chen ,  Chen-Ming Huang ,  Ya-Chen Kao

    IPC: G11C1600

    CPC classification number: G11C16/3418 ,  G11C16/0425

    Abstract: A method to suppress bit-line leakage in a nonvolatile memory cell is achieved. The method comprises providing an array of nonvolatile memory cells comprising source and bulk terminals. The array comprises a plurality of subarrays. The sources of all the nonvolatile cells in each subarray are coupled together to form a common subarray source. Bulks of all the nonvolatile cells in the array are coupled together to form a common array bulk. A first, non-zero voltage is forced between the common subarray source and the common array bulk for a first subarray that is selected for an access operation. A second, non-zero voltage is forced between the common subarray source and the common array bulk for a second subarray that is not selected for an access operation. The second, non-zero voltage inhibits bit line leakage in the second subarray.

    Abstract translation: 实现了在非易失性存储单元中抑制位线泄漏的方法。 该方法包括提供包括源极和体积端子的非易失性存储器单元的阵列。 阵列包括多个子阵列。 每个子阵列中的所有非易失性单元的源耦合在一起以形成公共的子阵列源。 阵列中所有非易失性单元的容量被耦合在一起以形成共同的阵列体。 对于为访问操作选择的第一子阵列，第一个非零电压被强制在公共子阵列源和公共阵列块之间。 第二个非零电压被强制在公共子阵列源和公共阵列块之间，用于未被选择用于访问操作的第二子阵列。 第二个非零电压禁止第二个子阵列中的位线泄漏。

    Semiconductor Test Structures
    26.
    发明申请
    Semiconductor Test Structures 有权
    半导体测试结构

    公开(公告)号：US20140203282A1

    公开(公告)日：2014-07-24

    申请号：US14246529

    申请日：2014-04-07

    Applicant: An-Chun Tu ,  Chen-Ming Huang ,  Chih-Jen Wu ,  Chin-Hsiang Lin

    Inventor： An-Chun Tu ,  Chen-Ming Huang ,  Chih-Jen Wu ,  Chin-Hsiang Lin

    IPC: G01R31/26

    CPC classification number: G01R31/2644 ,  G01R31/2884 ,  H01L22/14 ,  H01L22/32 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method performed using a resistive device, where the resistive device includes a substrate with an active region separated from a gate electrode by a dielectric and electrical contacts along a longest dimension of the gate electrode, the method comprising, performing one or more processes to form the resistive device, measuring a resistance between the electrical contacts, and correlating the measured resistance with a variation in one or more of the processes.

    Abstract translation: 一种使用电阻器件执行的方法，其中所述电阻器件包括具有通过栅电极的最长尺寸的电介质和电触点与栅电极分离的有源区的衬底，所述方法包括执行一个或多个工艺以形成 电阻器件，测量电触点之间的电阻，并将所测量的电阻与一个或多个过程中的变化相关联。

    Method for reducing contact resistance of CMOS image sensor
    27.
    发明授权
    Method for reducing contact resistance of CMOS image sensor 有权
    降低CMOS图像传感器接触电阻的方法

    公开(公告)号：US08586404B2

    公开(公告)日：2013-11-19

    申请号：US13556869

    申请日：2012-07-24

    Applicant: Kuan-Chieh Huang ,  Chih-Jen Wu ,  Chen-Ming Huang ,  Dun-Nian Yaung ,  An-Chun Tu

    Inventor： Kuan-Chieh Huang ,  Chih-Jen Wu ,  Chen-Ming Huang ,  Dun-Nian Yaung ,  An-Chun Tu

    IPC: H01L21/00

    CPC classification number: H01L27/14689 ,  H01L21/28518

    Abstract: This description relates to a method for reducing CMOS Image Sensor (CIS) contact resistance, the CIS having a pixel array and a periphery. The method includes performing Physical Vapor Deposition (PVD) at a pixel contact hole area, annealing for silicide formation at the pixel contact hole area and performing contact filling. This description also relates to a method for reducing CMOS Image Sensor (CIS) contact resistance, the CIS having a pixel array and a periphery. The method includes implanting N+ or P+ for pixel contact plugs at a pixel contact hole area, performing Physical Vapor Deposition (PVD) at pixel contact hole area, annealing for silicide formation at the pixel contact hole area, performing contact filling and depositing a first metal film layer, wherein the first metal film layer links contact holes for a source, a drain, or a poly gate of a CMOS device.

    Abstract translation: 本说明书涉及用于降低CMOS图像传感器（CIS）接触电阻的方法，CIS具有像素阵列和周边。 该方法包括在像素接触孔区域进行物理气相沉积（PVD），在像素接触孔区域进行硅化物形成退火并进行接触填充。 该描述还涉及用于减小CMOS图像传感器（CIS）接触电阻的方法，CIS具有像素阵列和周边。 该方法包括在像素接触孔区域处对像素接触插塞注入N +或P +，在像素接触孔区域进行物理气相沉积（PVD），在像素接触孔区域进行硅化物形成退火，执行接触填充和沉积第一金属 膜层，其中所述第一金属膜层连接CMOS器件的源极，漏极或多晶硅栅极的接触孔。

    Semiconductor Test Structures
    28.
    发明申请
    Semiconductor Test Structures 有权
    半导体测试结构

    公开(公告)号：US20130076385A1

    公开(公告)日：2013-03-28

    申请号：US13241634

    申请日：2011-09-23

    Applicant: An-Chun Tu ,  Chen-Ming Huang ,  Chih-Jen Wu ,  Chin-Hsiang Lin

    Inventor： An-Chun Tu ,  Chen-Ming Huang ,  Chih-Jen Wu ,  Chin-Hsiang Lin

    IPC: G01R1/067

    CPC classification number: G01R31/2644 ,  G01R31/2884 ,  H01L22/14 ,  H01L22/32 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A resistive test structure that includes a semiconductor substrate with an active region, a gate stack formed over the active region, a first electrical contact in communication with the active region on opposing sides of the gate stack, the first electrical contact providing an electrical short across a first dimension of the gate stack, and a second electrical contact in communication with the active region on the opposing sides of the gate stack, the second electrical contact providing an electrical short across the first dimension of the gate stack, the first and second electrical contacts spaced along a second dimension of the gate stack perpendicular to the first dimension.

    Abstract translation: 一种电阻测试结构，其包括具有有源区的半导体衬底，形成在有源区上的栅极叠层，与栅极堆叠的相对侧上的有源区连通的第一电触点，第一电触点提供跨越 栅极堆叠的第一尺寸和与栅极堆叠的相对侧上的有源区域连通的第二电触点，第二电触点跨过栅极堆叠的第一维度提供电短路，第一和第二电极 接触件沿垂直于第一尺寸的栅极堆叠的第二尺寸间隔开。

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