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    FinFET device and method of manufacturing same
    21.
    发明授权
    FinFET device and method of manufacturing same 有权
    FinFET器件及其制造方法

    公开(公告)号：US08624326B2

    公开(公告)日：2014-01-07

    申请号：US13277669

    申请日：2011-10-20

    申请人： Chi-Ming Chen ,  Chung-Yi Yu ,  Ho-Yung David Hwang

    发明人： Chi-Ming Chen ,  Chung-Yi Yu ,  Ho-Yung David Hwang

    IPC分类号： H01L21/70

    CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/785

    摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a first dielectric layer disposed over the substrate. The semiconductor device further includes a buffer layer disposed over the substrate and between first and second walls of a trench of the dielectric layer. The semiconductor device further includes an insulator layer disposed over the buffer layer and between the first and second wall of the trench of the dielectric layer. The semiconductor device also includes a second dielectric layer disposed over the first dielectric layer and the insulator layer. Further, the semiconductor device includes a fin structure disposed over the insulator layer and between first and second walls of a trench of the second dielectric layer.

    摘要翻译： 公开了一种用于制造半导体器件的半导体器件和方法。 示例性的半导体器件包括：衬底，包括设置在衬底上的第一介电层。 该半导体器件还包括一个缓冲层，该缓冲层设置在该衬底上并且位于介电层沟槽的第一和第二壁之间。 半导体器件还包括设置在缓冲层之上并位于介电层沟槽的第一和第二壁之间的绝缘体层。 半导体器件还包括设置在第一介电层和绝缘体层之上的第二电介质层。 此外，半导体器件包括布置在绝缘体层之上以及第二介电层的沟槽的第一和第二壁之间的翅片结构。

    SILICON WAFER STRENGTH ENHANCEMENT
    22.
    发明申请
    SILICON WAFER STRENGTH ENHANCEMENT 有权
    硅胶强度增强

    公开(公告)号：US20120168911A1

    公开(公告)日：2012-07-05

    申请号：US12982275

    申请日：2010-12-30

    申请人： Chi-Ming Chen ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Ho-Yung David Hwang ,  Alexander Kalnitsky

    发明人： Chi-Ming Chen ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Ho-Yung David Hwang ,  Alexander Kalnitsky

    IPC分类号： H01L29/30 ,  H01L29/20 ,  H01L21/322

    CPC分类号： H01L21/3225

    摘要： Provided is a method of fabricating a semiconductor device. The method includes: receiving a silicon wafer that contains oxygen; forming a zone in the silicon wafer, the zone being substantially depleted of oxygen; causing a nucleation process to take place in the silicon wafer to form oxygen nuclei in a region of the silicon wafer outside the zone; and growing the oxygen nuclei into defects. Also provided is an apparatus that includes a silicon wafer. The silicon wafer includes: a first portion that is substantially free of oxygen, the first portion being disposed near a surface of the silicon wafer; and a second portion that contains oxygen; wherein the second portion is at least partially surrounded by the first portion.

    摘要翻译： 提供一种制造半导体器件的方法。 该方法包括：接收含有氧的硅晶片; 在硅晶片中形成区域，该区域基本上耗尽氧气; 导致在硅晶片中发生成核过程，以在区域外的硅晶片的区域中形成氧核; 并将氧原子生长成缺陷。 还提供了一种包括硅晶片的设备。 硅晶片包括：基本上不含氧的第一部分，第一部分设置在硅晶片的表面附近; 和含有氧的第二部分; 其中所述第二部分至少部分地被所述第一部分包围。

    REDUCING WAFER DISTORTION THROUGH A LOW CTE LAYER
    23.
    发明申请
    REDUCING WAFER DISTORTION THROUGH A LOW CTE LAYER 有权
    通过低CTE层减少波浪失真

    公开(公告)号：US20120138945A1

    公开(公告)日：2012-06-07

    申请号：US12959984

    申请日：2010-12-03

    申请人： Chi-Ming Chen ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Ho-Yung David Hwang

    发明人： Chi-Ming Chen ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Ho-Yung David Hwang

    IPC分类号： H01L29/20 ,  H01L21/20

    CPC分类号： H01L29/7786 ,  H01L21/76254 ,  H01L29/2003 ,  H01L29/267

    摘要： Provided is a method of fabricating a semiconductor device. The method includes forming a first layer on a first side of a first silicon wafer. The first silicon wafer has a second side opposite the first side. The first layer has a coefficient-of-thermal-expansion (CTE) that is lower than that of silicon. The method includes bonding the first wafer to a second silicon wafer in a manner so that the first layer is disposed in between the first and second silicon wafers. The method includes removing a portion of the first silicon wafer from the second side. The method includes forming a second layer over the second side of the first silicon wafer. The second layer has a CTE higher than that of silicon.

    摘要翻译： 提供一种制造半导体器件的方法。 该方法包括在第一硅晶片的第一侧上形成第一层。 第一硅晶片具有与第一侧相对的第二侧。 第一层的热膨胀系数（CTE）低于硅的热膨胀系数。 该方法包括以使得第一层被布置在第一和第二硅晶片之间的方式将第一晶片接合到第二硅晶片。 该方法包括从第二侧去除第一硅晶片的一部分。 该方法包括在第一硅晶片的第二侧上形成第二层。 第二层具有高于硅的CTE。

    Technique for smoothing an interface between layers of a semiconductor device
    24.
    发明授权
    Technique for smoothing an interface between layers of a semiconductor device 有权
    用于平滑半导体器件的层之间的界面的技术

    公开(公告)号：US08772845B2

    公开(公告)日：2014-07-08

    申请号：US13240714

    申请日：2011-09-22

    申请人： Chih-Ming Chen ,  Cheng-Yuan Tsai ,  Chung-Yi Yu ,  Kai-Wen Cheng ,  Kuo-Ming Wu

    发明人： Chih-Ming Chen ,  Cheng-Yuan Tsai ,  Chung-Yi Yu ,  Kai-Wen Cheng ,  Kuo-Ming Wu

    IPC分类号： H01L21/02

    CPC分类号： H01L27/228 ,  H01L43/08 ,  H01L43/12

    摘要： The present disclosure provides a semiconductor memory device. The device includes a pinning layer having an anti-ferromagnetic material and disposed over a first electrode; a pinned layer disposed over the pinning layer; a composite layer disposed over the pinned layer, the composite layer having a magnetic material randomly distributed in a non-magnetic material; a barrier layer disposed on the composite layer; a free layer disposed over the barrier layer; and a second electrode disposed over the free layer.

    摘要翻译： 本公开提供一种半导体存储器件。 该装置包括具有反铁磁材料并设置在第一电极上的钉扎层; 设置在钉扎层上方的钉扎层; 复合层，其设置在所述被钉扎层上方，所述复合层具有随机分布在非磁性材料中的磁性材料; 设置在所述复合层上的阻挡层; 设置在阻挡层上的自由层; 以及设置在所述自由层上方的第二电极。

    FORMING A PROTECTIVE FILM ON A BACK SIDE OF A SILICON WAFER IN A III-V FAMILY FABRICATION PROCESS
    26.
    发明申请
    FORMING A PROTECTIVE FILM ON A BACK SIDE OF A SILICON WAFER IN A III-V FAMILY FABRICATION PROCESS 有权
    在III-V家族制造工艺中形成硅片背面的保护膜

    公开(公告)号：US20130078783A1

    公开(公告)日：2013-03-28

    申请号：US13244340

    申请日：2011-09-24

    申请人： Chun-Feng Nieh ,  Chung-Yi Yu ,  Hung-Ta Lin

    发明人： Chun-Feng Nieh ,  Chung-Yi Yu ,  Hung-Ta Lin

    IPC分类号： H01L21/762

    CPC分类号： H01L21/76224

    摘要： Provided is a method of fabricating a semiconductor device. The method includes forming a first dielectric layer over a first surface and a second surface of a silicon substrate. the first and second surfaces being opposite surfaces. A first portion of the first dielectric layer covers the first surface of the substrate, and a second portion of the first dielectric layer covers the second surface of the substrate. The method includes forming openings that extend into the substrate from the first surface. The method includes filling the openings with a second dielectric layer. The method includes removing the first portion of the first dielectric layer without removing the second portion of the first dielectric layer.

    摘要翻译： 提供一种制造半导体器件的方法。 该方法包括在硅衬底的第一表面和第二表面上形成第一电介质层。 第一和第二表面是相对的表面。 第一介电层的第一部分覆盖基板的第一表面，并且第一介电层的第二部分覆盖基板的第二表面。 该方法包括形成从第一表面延伸到基底中的开口。 该方法包括用第二介电层填充开口。 该方法包括在不去除第一介电层的第二部分的情况下去除第一介电层的第一部分。

    CMOS IMAGE SENSOR AND METHOD FOR MANUFACTURING SAME
    29.
    发明申请
    CMOS IMAGE SENSOR AND METHOD FOR MANUFACTURING SAME 审中-公开
    CMOS图像传感器及其制造方法

    公开(公告)号：US20090189233A1

    公开(公告)日：2009-07-30

    申请号：US12020149

    申请日：2008-01-25

    申请人： Jen-Cheng Liu ,  Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Chi-Hsin Lo ,  Feng-Jia Shiu ,  Chung-Yi Yu

    发明人： Jen-Cheng Liu ,  Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Chi-Hsin Lo ,  Feng-Jia Shiu ,  Chung-Yi Yu

    IPC分类号： H01L31/0232 ,  H01L31/18

    CPC分类号： H01L27/14625 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14685

    摘要： An optical image sensor is fabricated by forming a pixel array and a peripheral region surrounding the pixel array on a semiconductor substrate, the peripheral region containing peripheral circuitry. An inter-level-dielectric layer is formed over the substrate and a plurality of interconnect wiring layers are formed over the inter-level-dielectric layer. Each interconnect wiring layer includes interconnecting metal features and a layer of inter-level-dielectric material covering the interconnecting metal features. The plurality of interconnect wiring layers are provided in a manner that there are N levels of wiring layers in the peripheral region and 1 to (N−1) levels of wiring layers over the pixel array. An etch-stop layer is formed over the top-most level interconnecting metal features in the peripheral region.

    摘要翻译： 通过在半导体衬底上形成围绕像素阵列的像素阵列和外围区域来制造光学图像传感器，该外围区域包含外围电路。 层间电介质层形成在衬底之上，并且在层间电介质层之上形成多个互连布线层。 每个互连布线层包括互连金属特征和覆盖互连金属特征的层间电介质材料层。 多个互连布线层的设置方式是在像素阵列的周边区域中有N层布线层和布线层的1层（N-1）层。 在外围区域中最顶层的互连金属特征上形成蚀刻停止层。

    Split-gate memory cells and fabrication methods thereof
    30.
    发明申请
    Split-gate memory cells and fabrication methods thereof 有权
    分离栅存储单元及其制造方法

    公开(公告)号：US20080121975A1

    公开(公告)日：2008-05-29

    申请号：US11592290

    申请日：2006-11-03

    申请人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

    发明人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

    IPC分类号： H01L29/788

    CPC分类号： H01L27/115 ,  H01L27/11521

    摘要： Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A pair of floating gates are disposed on the active regions and self-aligned with the isolation regions, wherein a top level of the floating gate is equal to a top level of the isolation regions. A pair of control gates are self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates are disposed on the outer sidewalls of the pair of control gates along the second direction.

    摘要翻译： 分离栅存储单元及其制造方法。 分离栅极存储单元包括沿着第一方向形成在半导体衬底上的多个隔离区域，在限定具有一对漏极和源极区域的有源区域的两个相邻隔离区域之间。 一对浮置栅极设置在有源区上并与隔离区自对准，其中浮置栅极的顶层等于隔离区的顶层。 一对控制栅极与浮动栅极自对准并沿着第二方向设置在浮动栅极上。 源极线沿第二方向设置在该对控制栅极之间。 一对选择栅极沿着第二方向设置在该对控制栅极的外侧壁上。