公开(公告)号：US5665991A

公开(公告)日：1997-09-09

申请号：US456238

申请日：1995-05-31

申请人： Taylor R. Efland ,  Satwinder Malhi ,  Michael C. Smayling ,  Joseph A. Devore ,  Ross E. Teggatz ,  Alec J. Morton

发明人： Taylor R. Efland ,  Satwinder Malhi ,  Michael C. Smayling ,  Joseph A. Devore ,  Ross E. Teggatz ,  Alec J. Morton

IPC分类号： H01L23/482 ,  H01L23/528 ,  H01L29/417 ,  H01L29/78 ,  H01L23/522

CPC分类号： H01L23/5286 ,  H01L23/4824 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2924/0002

摘要： The device has a semiconductor chip having active circuitry in the face thereof. The circuitry has busing over it containing two conductive layers having a plurality of contacts and vias with spacings between them that alternate with respect to one another to provide current ballasting and improved switching uniformity. The spacings between the alternating contacts and vias provide regions of maximum conductor thickness and therefore reduces the busing resistance. Staggering the rows of alternating contacts and vias provides further current ballasting. A first conducting layer is used to contact and provide electrically isolated low resistive conducting paths to the various semiconductor regions while the second conducting region is used to provide selective contact to the first conductive layer, thus providing a means of busing large currents over active semiconductor area without sacrificing performance parameters.

摘要翻译： 该器件具有在其表面上具有有源电路的半导体芯片。 该电路具有引线，其中包含两个具有多个触点的导电层和在它们之间具有相互间交替的间隙的通孔，以提供电流镇流和改善的开关均匀性。 交替触点和通孔之间的间距提供最大导体厚度的区域，因此降低了阻抗。 交错的交替触点和通孔的排列提供了进一步的电流镇流。 第一导电层用于接触并提供到各种半导体区域的电隔离的低电阻导电路径，而第二导电区域用于提供与第一导电层的选择性接触，从而提供在有源半导体区域上引入大电流的装置 而不牺牲性能参数。

公开(公告)号：US5640034A

公开(公告)日：1997-06-17

申请号：US883985

申请日：1992-05-18

申请人： Satwinder Malhi

发明人： Satwinder Malhi

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L29/7809 ,  H01L29/42368 ,  H01L29/7813 ,  H01L29/7834

摘要： A top drain trench based RESURF DMOS (reduced surface field double diffused MOS) transistor structure provides improved RDSon performance by minimizing transistor cell pitch. The transistor includes a gate, a source and drain. The trench may include a nonuniform dielectric lining. A drain drift region partially surrounds the trench. Current flows laterally enabling multiple trench based RESURF DMOS transistors to be formed on a single semiconductor die. The addition of an isolation region to electrically isolate the source from the substrate allows the power transistor to be incorporated into high side driver applications as well as other application mandating electrical isolation between the source and ground.

摘要翻译： 基于顶漏沟槽的RESURF DMOS（减小的表面场双扩散MOS）晶体管结构通过最小化晶体管单元间距来提供改善的RDSon性能。 晶体管包括栅极，源极和漏极。 沟槽可以包括不均匀的电介质衬里。 漏极漂移区域部分地围绕沟槽。 电流横向流动，使得能够在单个半导体管芯上形成多个基于沟槽的RESURF DMOS晶体管。 添加隔离区以将源极与衬底电隔离允许将功率晶体管并入高侧驱动器应用以及强制源极和地之间的电隔离的其他应用。

公开(公告)号：US5578514A

公开(公告)日：1996-11-26

申请号：US241543

申请日：1994-05-12

申请人： Oh-Kyong Kwon ,  Taylor R. Efland ,  Satwinder Malhi ,  Wai T. Ng

发明人： Oh-Kyong Kwon ,  Taylor R. Efland ,  Satwinder Malhi ,  Wai T. Ng

IPC分类号： H01L29/08 ,  H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66681 ,  H01L29/7801 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/0847 ,  H01L29/0878 ,  Y10S148/096

摘要： A transistor (10) has a thin epitaxial layer (14) of a second conductivity type on a semiconductor substrate (12) of a first conductivity type. A drift region (24) of the second conductivity type is formed extending through the thin epitaxial layer (14) to the substrate (12). A thick insulator layer (26) is formed on the drift region (24). An IGFET body (28) of the first conductivity type is formed adjacent the drift region (24). A source region (34) of the second conductivity type is formed within the IGFET body (28) and spaced from the drift region (24) defining a channel region (40) within the IGFET body (28). A conductive gate (32) is insulatively disposed over the IGFET body (28) and extends from the source region (34) to the thick insulator layer (26). A drain region (36) is formed adjacent the drift region (24).

摘要翻译： 晶体管（10）在第一导电类型的半导体衬底（12）上具有第二导电类型的薄外延层（14）。 形成第二导电类型的漂移区（24），延伸穿过薄外延层（14）到衬底（12）。 在漂移区（24）上形成厚的绝缘体层（26）。 第一导电类型的IGFET体（28）形成在漂移区（24）附近。 第二导电类型的源极区域（34）形成在IGFET主体（28）内并且与漂移区域（24）间隔开，从而限定IGFET体（28）内的沟道区域（40）。 导电栅极（32）被绝缘地设置在IGFET主体（28）上并且从源极区域（34）延伸到厚的绝缘体层（26）。 在漂移区（24）附近形成漏区（36）。

公开(公告)号：US5486484A

公开(公告)日：1996-01-23

申请号：US255023

申请日：1994-07-25

申请人： Satwinder Malhi

发明人： Satwinder Malhi

IPC分类号： H01L29/78 ,  H01L27/06 ,  H01L29/24 ,  H01L29/423 ,  H01L21/443

CPC分类号： H01L29/1608 ,  H01L27/0605 ,  H01L29/42368 ,  Y10S438/931

摘要： A MOSFET device (100) having a silicon carbide substrate (102). A channel region (106) of a first conductivity type and an epitaxial layer (104) of a second conductivity type are located above the silicon carbide substrate (102). First and second source/drain regions (118), also of the first conductivity type are located directly within the channel region (106). No well region is placed between the first and second source/drain regions (118) and the channel region (106). A gate (120) is separated from the channel region (106) by an insulator layer (110). Insulator layer (110) has a thin portion (114) and a thick portion (116).

公开(公告)号：US5349207A

公开(公告)日：1994-09-20

申请号：US20820

申请日：1993-02-22

申请人： Satwinder Malhi

发明人： Satwinder Malhi

IPC分类号： H01L21/20 ,  H01L21/762 ,  H01L29/10 ,  H01L29/24 ,  H01L29/786 ,  H01L29/161

CPC分类号： H01L29/1608 ,  H01L21/2007 ,  H01L21/762 ,  H01L29/1079 ,  H01L29/78684 ,  Y10S148/148 ,  Y10S438/931

摘要： A silicon carbide structure (10) and method capable of using existing silicon wafer fabrication facilities. A silicon wafer (20) is provided which has a first diameter. At least one silicon carbide wafer (30) is provided which has a given width and length (or diameter). The width and length (or diameter) of the silicon carbide wafer (30) are smaller than the diameter of the silicon wafer (20). The silicon wafer (20) and the silicon carbide wafer (30) are then bonded together. The bonding layer (58) may comprise silicon germanium, silicon dioxide, silicate glass or other materials. Structures such as MOSFET (62) may be then formed in silicon carbide wafer (30).

摘要翻译： 一种能够使用现有的硅晶片制造设备的碳化硅结构（10）和方法。 提供具有第一直径的硅晶片（20）。 提供至少一个具有给定宽度和长度（或直径）的碳化硅晶片（30）。 碳化硅晶片（30）的宽度和长度（或直径）小于硅晶片（20）的直径。 然后将硅晶片（20）和碳化硅晶片（30）接合在一起。 结合层（58）可以包括硅锗，二氧化硅，硅酸盐玻璃或其它材料。 然后可以在碳化硅晶片（30）中形成诸如MOSFET（62）的结构。

公开(公告)号：US5172208A

公开(公告)日：1992-12-15

申请号：US722376

申请日：1991-06-25

申请人： Satwinder Malhi

发明人： Satwinder Malhi

IPC分类号： H01L29/74 ,  H01L29/745

CPC分类号： H01L29/7455 ,  H01L29/7436

摘要： A thyristor (38) is formed over an insulating layer (44). A gate (70) is operable to create a depletion region through the semiconductor layer (46) in which the thyristor (38) is implemented in order to turn the thyristor off. Isolation regions (48, 52) prevent operation of the thyristor from affecting adjacent devices.

摘要翻译： 在绝缘层（44）上形成晶闸管（38）。 栅极（70）可操作以通过其中实施晶闸管（38）的半导体层（46）产生耗尽区，以便关断晶闸管。 隔离区域（48,52）防止晶闸管的操作影响相邻的设备。

公开(公告)号：US5059897A

公开(公告)日：1991-10-22

申请号：US447328

申请日：1989-12-07

申请人： Thomas J. Aton ,  Satwinder Malhi ,  Masashi Hashimoto ,  Shivaling S. Mahant-Shitti ,  Oh-Kyong Kwon ,  Thirumalai Sridhar

发明人： Thomas J. Aton ,  Satwinder Malhi ,  Masashi Hashimoto ,  Shivaling S. Mahant-Shitti ,  Oh-Kyong Kwon ,  Thirumalai Sridhar

IPC分类号： G01R31/28 ,  H01L21/66

CPC分类号： G01R31/281

摘要： A system and method for testing the continuity of interconnecting nets on a substrate to be used in multi-chip technology is provided. The system includes coupling a test pad (15) to the net (12) to be tested. The test pad (15) is coupled through a diode (34) to a common node (32). The voltage of a first node (16) of the net (12) is sensed by a voltmeter (38) which is coupled to ground. A predetermined current signal is applied to each node (16, 18, 20, 22) in the net through the use of a probe (42). The voltage of the remaining nets (14) is sensed by a voltmeter (44). If an erroneous interconnection (31) is present between the net (12) to be tested and any other net (14) on the substrate, the voltage of the other net (14) will fluctuate. The voltmeter (38) will indicate if there is an electrical connection between the node (16) and the test pad (15) during testing. If an electrical path is established between each node in the net (12) and test pad (15), the continuity of the net (12) is established through the operation of Ohm's law.

摘要翻译： 提供了一种用于测试在多芯片技术中使用的基板上互连网络的连续性的系统和方法。 该系统包括将测试垫（15）耦合到要测试的网（12）。 测试焊盘（15）通过二极管（34）耦合到公共节点（32）。 网（12）的第一节点（16）的电压由耦合到地的电压计（38）感测。 通过使用探针（42）将预定电流信号施加到网中的每个节点（16,18,20,22）。 剩余网（14）的电压由电压计（44）感测。 如果要测试的网络（12）和基板上的任何其他网络（14）之间存在错误的互连（31），则另一个网络（14）的电压将波动。 电压表（38）将指示在测试期间节点（16）和测试垫（15）之间是否存在电气连接。 如果在网络（12）和测试板（15）中的每个节点之间建立电路径，则通过欧姆定律的操作建立网络（12）的连续性。

公开(公告)号：US5933320A

公开(公告)日：1999-08-03

申请号：US771178

申请日：1996-12-20

申请人： Satwinder Malhi

发明人： Satwinder Malhi

IPC分类号： G06F1/16 ,  G06F3/02 ,  H01H13/14

CPC分类号： G06F3/0221 ,  G06F1/1616 ,  G06F1/1666 ,  H01H2223/052

摘要： A notebook computer (10) including a keyboard (14) having gas or piston expandable keys (18) which may be placed in an expanded or compressed state. While in an expanded state, the keys (18) are approximately the size of the keys on a standard keyboard. While in a compressed state, the keys are essentially flat, allowing the keyboard to be folded upon itself. Accordingly, the keyboard (18) may be folded in a compressed state when the computer is not in use to reduce keyboard area, and unfolded and expanded to provide a full size keyboard when the computer is in use.

摘要翻译： 一种笔记本计算机（10），包括具有气体或活塞可扩张键（18）的键盘（14），所述钥匙可以放置在膨胀或压缩状态。 在扩展状态下，键（18）大约是标准键盘上的键的大小。 在处于压缩状态时，键基本上是平的，允许键盘折叠在自身上。 因此，当计算机不使用以减少键盘区域时，键盘（18）可以被折叠成压缩状态，并且在计算机使用时展开并扩展以提供全尺寸键盘。

公开(公告)号：US5656517A

公开(公告)日：1997-08-12

申请号：US473837

申请日：1995-06-07

申请人： Taylor R. Efland ,  Roy C. Jones, III ,  Oh-Kyong Kwon ,  Michael C. Smayling ,  Satwinder Malhi ,  Wai Tung Ng

发明人： Taylor R. Efland ,  Roy C. Jones, III ,  Oh-Kyong Kwon ,  Michael C. Smayling ,  Satwinder Malhi ,  Wai Tung Ng

IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/7816 ,  H01L29/0696 ,  H01L29/7802 ,  H01L29/42368

摘要： A source cell having reduced area and reduced polysilicon window width requirements for use as the source region in a DMOS transistor is disclosed, comprising: a source region of semiconductor material disposed on a semiconductor substrate; a plurality of backgate contact segments of predetermined size and separated by predetermined distances; and a plurality of source contact windows alternating with the backgate contact segments so that a narrow source contact region is formed of alternating source contact and backgate contact material. A DMOS transistor embodying the source region including the backgate contact segments and windowed source contacting regions of the invention is disclosed. An integrated circuit providing an array of DMOS transistors having the improved source regions of the invention is disclosed.Other devices, systems and methods are also disclosed.

摘要翻译： 公开了一种具有减小的面积和降低的多晶硅窗口宽度要求的源单元，用于DMOS晶体管中的源极区域，包括：设置在半导体衬底上的半导体材料的源极区域; 多个预定尺寸的后门接触片段并隔开预定距离; 以及多个源极接触窗与后盖接触片交替，使得窄的源极接触区域由交替的源极接触和后盖接触材料形成。 公开了体现源区域的DMOS晶体管，其包括本发明的背栅接触段和窗口源极接触区域。 公开了提供具有本发明改进的源极区域的DMOS晶体管阵列的集成电路。 还公开了其他装置，系统和方法。

公开(公告)号：US5539238A

公开(公告)日：1996-07-23

申请号：US939349

申请日：1992-09-02

申请人： Satwinder Malhi

发明人： Satwinder Malhi

IPC分类号： H01L21/316 ,  H01L21/225 ,  H01L21/336 ,  H01L21/76 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78 ,  H01L29/00 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/7835 ,  H01L29/0615 ,  H01L29/0653 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7809 ,  H01L29/7816 ,  H01L29/7834 ,  H01L21/2255 ,  H01L29/0847 ,  H01L29/41766 ,  Y10S148/126

摘要： A high voltage power transistor cell is developed that provides improved RDSon performance without sacrificing breakdown performance through utilization of trench based transistor technology. A source, drain and trench are formed within a substrate. A gate is formed on the surface over a spacing between the source and the trench. A drift region is formed around the trench. An isolation region may optionally be added allowing electrical isolation between the source and the substrate. The lateral current flow feature allows multiple high voltage power transistors, electrically isolated from one another, to exist on a single semiconductor chip. The drift region formed around the trench provides RESURF transistor characteristics without sacrificing die area.

摘要翻译： 开发了一种高电压功率晶体管单元，通过利用基于沟槽的晶体管技术，可以提供更好的RDSon性能，而不会牺牲击穿性能。 在衬底内形成源极，漏极和沟槽。 在源极和沟槽之间的间隔上的表面上形成栅极。 在沟槽周围形成漂移区域。 可以可选地添加隔离区域，允许源极和衬底之间的电隔离。 横向电流流动特征允许在单个半导体芯片上存在彼此电隔离的多个高压功率晶体管。 围绕沟槽形成的漂移区域提供RESURF晶体管特性，而不牺牲管芯面积。