公开(公告)号：US20100203689A1

公开(公告)日：2010-08-12

申请号：US12762427

申请日：2010-04-19

申请人： Kerry Bernstein ,  Edward J. Nowak ,  BethAnn Rainey

发明人： Kerry Bernstein ,  Edward J. Nowak ,  BethAnn Rainey

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L29/045 ,  H01L29/66795

摘要： A drive strength tunable FinFET, a method of drive strength tuning a FinFET, a drive strength ratio tuned FinFET circuit and a method of drive strength tuning a FinFET, wherein the FinFET has either at least one perpendicular and at least one angled fin or has at least one double-gated fin and one split-gated fin.

摘要翻译： 驱动强度可调谐FinFET，FinFET的驱动强度调谐方法，驱动强度比调谐FinFET电路和FinFET的驱动强度调谐方法，其中FinFET具有至少一个垂直和至少一个成角度的鳍或具有 最少一个双门翅和一个分闸门。

公开(公告)号：US07692944B2

公开(公告)日：2010-04-06

申请号：US12127086

申请日：2008-05-27

申请人： Kerry Bernstein ,  Paul W. Coteus ,  Philip G. Emma

发明人： Kerry Bernstein ,  Paul W. Coteus ,  Philip G. Emma

IPC分类号： G11C5/02

CPC分类号： H01L27/0688 ,  H01L21/6835 ,  H01L21/8221 ,  H01L27/105 ,  H01L27/1052 ,  H01L2221/68359 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105

摘要： An integrated circuit design, structure and method for fabrication thereof includes at least one logic device layer and at least two additional separate memory array layers. Each of the logic device layer and the at least two memory array layers is independently optimized for a particular type of logic device or memory device disposed therein. Preferably also disposed within the logic device layer are array sense amplifiers, memory array output drivers and like higher performance circuitry otherwise generally disposed within memory array layer substrates. All layers may be independently powered to provide additional performance enhancement.

摘要翻译： 其制造的集成电路设计，结构和方法包括至少一个逻辑器件层和至少两个额外的分开的存储器阵列层。 对于设置在其中的特定类型的逻辑设备或存储器件，逻辑器件层和至少两个存储器阵列层中的每一个被独立地优化。 优选地还设置在逻辑器件层内的是阵列读出放大器，存储器阵列输出驱动器和类似的高性能电路，否则通常设置在存储器阵列层衬底内。 所有层可以独立供电以提供额外的性能增强。

公开(公告)号：US20100052108A1

公开(公告)日：2010-03-04

申请号：US12201580

申请日：2008-08-29

申请人： John E. Barth, JR. ,  Kerry Bernstein

发明人： John E. Barth, JR. ,  Kerry Bernstein

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/481 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor structure includes at least one silicon substrate having first and second planar surfaces, and at least one through silicon via filled with a conductive material and extending vertically through the first planar surface of the at least one silicon substrate to the second planar surface thereof. The through silicon via forms a vertical interconnection between a plurality of electronic circuits and an amount of dielectric insulation surrounding the through silicon via is varied based on a defined function of the through silicon via.

摘要翻译： 半导体结构包括具有第一和第二平面表面的至少一个硅衬底，以及填充有导电材料并且至少穿过至少一个硅衬底的第一平坦表面垂直延伸到其第二平坦表面的至少一个穿硅通孔。 穿通硅通孔在多个电子电路之间形成垂直互连，并且围绕穿过硅通孔的绝缘绝缘体的量基于硅通孔的限定功能而变化。

公开(公告)号：US20100052100A1

公开(公告)日：2010-03-04

申请号：US12201462

申请日：2008-08-29

申请人： John E. Barth, JR. ,  Kerry Bernstein

发明人： John E. Barth, JR. ,  Kerry Bernstein

IPC分类号： H01L29/8605 ,  H01L21/02

CPC分类号： H01L29/861 ,  H01L21/761 ,  H01L21/76264 ,  H01L23/535 ,  H01L27/0255 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure is disclosed. The semiconductor structure includes a bulk substrate of a first polarity type, a buried insulator layer disposed on the bulk substrate, an active semiconductor layer disposed on top of the buried insulator layer including a shallow trench isolation region and a diffusion region of the first polarity type, a band region of a second polarity type disposed directly beneath the buried insulator layer and forming a conductive path, a well region of the second polarity type disposed in the bulk substrate and in contact with the band region, a deep trench filled with a conductive material of the first polarity type disposed within the well region, and an electrostatic discharge (ESD) protect diode defined by a junction between a lower portion of the deep trench and the well region.

摘要翻译： 公开了半导体结构。 半导体结构包括第一极性类型的体基板，设置在体基板上的掩埋绝缘体层，设置在包括浅沟槽隔离区域和第一极性类型的扩散区域的掩埋绝缘体层的顶部上的有源半导体层 设置在掩埋绝缘体层正下方并形成导电路径的第二极性类型的带区域，设置在本体衬底中并与带区接触的第二极性类型的阱区，填充有导电的深沟槽 设置在阱区内的第一极性类型的材料以及由深沟槽的下部和阱区之间的接合部限定的静电放电（ESD）保护二极管。

公开(公告)号：US07642813B2

公开(公告)日：2010-01-05

申请号：US11850857

申请日：2007-09-06

申请人： Kerry Bernstein ,  Philip G. Emma ,  John A. Fifield ,  Paul D. Kartschoke ,  William A. Klaasen ,  Norman J. Rohrer

发明人： Kerry Bernstein ,  Philip G. Emma ,  John A. Fifield ,  Paul D. Kartschoke ,  William A. Klaasen ,  Norman J. Rohrer

IPC分类号： H03K19/20 ,  H03K19/094 ,  H03K19/003

CPC分类号： H03K19/007

摘要： The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors. Also, there is provided a design structure embodied in a machine readable medium used in a design process, and which includes such error correcting logic system.

摘要翻译： 本发明包括纠错逻辑系统，其允许仅使用一个冗余单元来硬化关键电路并且不损失电路性能。 该系统提供互连门，其抑制馈送到互连门的至少两个冗余动态逻辑门之一的故障。 该系统适用于动态或静态逻辑系统。 该系统防止故障传播，不仅解决软错误，而且还会引起噪声引起的错误。 此外，提供了在设计过程中使用的机器可读介质中体现的设计结构，并且包括这种纠错逻辑系统。

公开(公告)号：US20090141527A1

公开(公告)日：2009-06-04

申请号：US11949063

申请日：2007-12-03

申请人： Igor Arsovski ,  Kerry Bernstein

发明人： Igor Arsovski ,  Kerry Bernstein

IPC分类号： G11C15/04

CPC分类号： G11C15/04

摘要： A content addressable memory (CAM) device includes an array of memory cells arranged in rows in a word line direction and columns arranged in a bit line direction, and compare circuitry configured to compare data presented to the array with data stored in each row and column of the array, and simultaneously indicate match results on each row and column of the array, thereby resulting in a two-dimensional, matrix-based data comparison operation.

摘要翻译： 一种内容可寻址存储器（CAM）装置，包括排列成字线方向的存储单元阵列和排列在位线方向上的列，以及比较电路，被配置为将呈现给阵列的数据与存储在每行和列中的数据进行比较 并且同时指示阵列的每一行和列上的匹配结果，从而导致二维的基于矩阵的数据比较操作。

公开(公告)号：US20090085152A1

公开(公告)日：2009-04-02

申请号：US11865079

申请日：2007-10-01

申请人： Kerry Bernstein ,  Timothy J. Dalton ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Stephen E. Luce ,  Anthony K. Stamper

发明人： Kerry Bernstein ,  Timothy J. Dalton ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Stephen E. Luce ,  Anthony K. Stamper

IPC分类号： H01L23/62 ,  H01L21/44

CPC分类号： H01L23/5256 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

摘要： Three dimensional vertical e-fuse structures and methods of manufacturing the same are provided herein. The method of forming a fuse structure comprises providing a substrate including an insulator layer and forming an opening in the insulator layer. The method further comprises forming a conductive layer along a sidewall of the opening and filling the opening with an insulator material. The vertical e-fuse structure comprises a first contact layer and a second contact layer. The structure further includes a conductive material lined within a via and in electrical contact with the first contact layer and the second contact layer. The conductive material has an increased resistance as a current is applied thereto.

摘要翻译： 本文提供三维垂直电子熔丝结构及其制造方法。 形成熔丝结构的方法包括提供包括绝缘体层并在绝缘体层中形成开口的衬底。 该方法还包括沿着开口的侧壁形成导电层并用绝缘体材料填充开口。 垂直e熔丝结构包括第一接触层和第二接触层。 该结构还包括衬里在通孔内并与第一接触层和第二接触层电接触的导电材料。 当施加电流时，导电材料具有增加的电阻。

公开(公告)号：US20080288720A1

公开(公告)日：2008-11-20

申请号：US11750676

申请日：2007-05-18

申请人： Jagreet S. Atwal ,  Joseph S. Barnes ,  Kerry Bernstein ,  Robert J. Bucki ,  Jason A. Cox

发明人： Jagreet S. Atwal ,  Joseph S. Barnes ,  Kerry Bernstein ,  Robert J. Bucki ,  Jason A. Cox

IPC分类号： G06F12/00 ,  G11C15/04 ,  H01L21/8239

CPC分类号： H01L25/18 ,  G06F12/0895 ,  G06F12/1027 ,  G11C15/00 ,  G11C15/04 ,  H01L27/1203 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multi-wafer CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-wafer CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the inventive CAM cell can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-wafer CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays.

摘要翻译： 提供了一种多晶圆CAM单元，其中增加行程距离的负面影响已经大大减少。 本发明通过利用三维积分实现多晶片CAM单元，其中多个有源电路层是垂直堆叠的并且垂直排列的互连件用于将来自堆叠层之一的器件连接到另一堆叠层中的另一器件 。 通过垂直堆叠具有垂直排列的互连的多个有源电路层，可以在主数据存储单元上方或下方的单独的层上实现本发明的CAM单元的每个比较端口。 这允许多晶片CAM结构在与标准随机存取存储器（RAM）单元相同的区域覆盖范围内实现，从而最小化数据访问并匹配比较延迟。

公开(公告)号：US20080283995A1

公开(公告)日：2008-11-20

申请号：US11750631

申请日：2007-05-18

申请人： Robert J. Bucki ,  Jagreet S. Atwal ,  Joseph S. Barnes ,  Kerry Bernstein ,  Eric Robinson

发明人： Robert J. Bucki ,  Jagreet S. Atwal ,  Joseph S. Barnes ,  Kerry Bernstein ,  Eric Robinson

IPC分类号： H01L23/52

CPC分类号： H01L25/0657 ,  G11C15/00 ,  H01L21/6835 ,  H01L24/24 ,  H01L24/82 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/1203 ,  H01L2221/68368 ,  H01L2224/24226 ,  H01L2224/80896 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/04953 ,  H01L2924/10329 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

摘要： A multi-ported CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-ported CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the multi-port CAM can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-port CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays. Each compare match line and data bit line has the length associated with a simple two-dimensional Static Random Access Memory (SRAM) cell array.

摘要翻译： 提供了一种多移动CAM单元，其中增加行程距离的负面影响已经大大减少。 多端口CAM单元在本发明中通过利用三维积分来实现，其中多个有源电路层是垂直堆叠的并且垂直对准的互连被用于将设备从堆叠层之一连接到另一层叠层中的另一个设备 。 通过垂直堆叠具有垂直排列的互连的多个有源电路层，多端口CAM的每个比较端口可以在主数据存储单元上方或下方的单独层上实现。 这允许在与标准随机存取存储器（RAM）单元相同的区域覆盖范围内实现多端口CAM结构，使数据访问最小化并匹配比较延迟。 每个比较匹配线和数据位线具有与简单的二维静态随机存取存储器（SRAM）单元阵列相关联的长度。

公开(公告)号：US07408798B2

公开(公告)日：2008-08-05

申请号：US11278189

申请日：2006-03-31

申请人： Kerry Bernstein ,  Paul W. Coteus ,  Philip G. Emma

发明人： Kerry Bernstein ,  Paul W. Coteus ,  Philip G. Emma

IPC分类号： G11C5/02

CPC分类号： H01L27/0688 ,  H01L21/6835 ,  H01L21/8221 ,  H01L27/105 ,  H01L27/1052 ,  H01L2221/68359 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105

摘要： An integrated circuit design, structure and method for fabrication Thereof includes at least one logic device layer and at least two additional separate memory array layers. Each of the logic device layer and the at least two memory array layers is independently optimized for a particular type of logic device or memory device disposed therein. Preferably also disposed within the logic device layer are array sense amplifiers, memory array output drivers and like higher performance circuitry otherwise generally disposed within memory array layer substrates. All layers may be independently powered to provide additional performance enhancement.

摘要翻译： 其制造的集成电路设计，结构和方法包括至少一个逻辑器件层和至少两个附加的独立存储器阵列层。 对于设置在其中的特定类型的逻辑设备或存储器件，逻辑器件层和至少两个存储器阵列层中的每一个被独立地优化。 优选地还设置在逻辑器件层内的是阵列读出放大器，存储器阵列输出驱动器和类似的高性能电路，否则通常设置在存储器阵列层衬底内。 所有层可以独立供电以提供额外的性能增强。