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公开(公告)号：US10956546B2
公开(公告)日：2021-03-23
申请号：US16000189
申请日：2018-06-05
Inventor： John Paul Lesso
Abstract: Embodiments of the disclosure provide a mechanism for performing a biometric algorithm on ear biometric data acquired from a user. The mechanism may be used for biometric authentication, or in-ear detect, for example. In one embodiment, a method is provided in which a quality metric of an input signal to a transducer and/or a signal on a return path from the transducer is monitored. One or more steps of a biometric process, comprising monitoring of a parameter related to an admittance of the transducer, comparison of the parameter to a stored profile for an authorised user, generation of a score based on the comparison, comparison of the score to one or more threshold values, and initiation of one or more actions, may be performed responsive to the quality metric meeting one or more criteria.
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公开(公告)号：US10923128B2
公开(公告)日：2021-02-16
申请号：US16115654
申请日：2018-08-29
Inventor： John Paul Lesso
Abstract: A method of performing speech recognition, comprises, at a first device: receiving an audio signal representing speech; performing a first data integrity check operation on the received audio signal; performing a speaker recognition process on the received audio signal; forwarding the received audio signal to a second device, wherein the second device comprises a speech recognition function; and forwarding an output of the first data integrity check operation to the second device. The method further comprises, at the second device: receiving the audio signal forwarded from the first device; receiving the output of the first data integrity check operation forwarded from the first device; performing a second data integrity check operation on the audio signal forwarded from the first device; and using a result of performing the speech recognition function on the audio signal forwarded from the first device only if an output of the second data integrity check operation matches the output of the first data integrity check operation forwarded from the first device.
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公开(公告)号：US10574256B1
公开(公告)日：2020-02-25
申请号：US16141555
申请日：2018-09-25
Inventor： John Paul Lesso
Abstract: This application relates to time-encoding modulators (TEMs). A TEM (100) receives an input signal (SIN) and outputs a time-encoded output signal (SOUT). A filter arrangement (102) receives the input signal and also a feedback signal (SFB) from the TEM output, and generates a filtered signal (SFIL) based, at least in part, on the feedback signal. A comparator (101) receives the filtered signal and outputs a time-encoded signal (SPWM) based at least in part on the filtered signal. The time encoding modulator is operable in a first mode with the filter arrangement configured as an active filter and in a second mode with the filter arrangement configured as a passive filter. The filter arrangement may include an op-amp (103), capacitance (104) and switch network (105). In the first mode the op-amp (103) is enabled, and coupled with the capacitance (104) to provide the active filter. In the second mode the op-amp (103) is disabled and the capacitance coupled to a signal path for the feedback signal to provide a passive filter.
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公开(公告)号：US10566992B2
公开(公告)日：2020-02-18
申请号：US16375868
申请日：2019-04-05
Inventor： John Paul Lesso
IPC: H03M3/00 , H03K21/38 , H03K3/0233 , H03M1/50 , H03K7/08
Abstract: This application relates to time-encoding modulators (301,700) having a self-oscillating modulator module configured to receive an input signal and output a pulse-width modulated signal (SPWM) where the pulse-width modulated signal is synchronised to a first clock signal (CLK1). A hysteretic comparator module (302) located in a feedforward path is configured to generate the time encoded signal (SPWM) at a first node (304) based on the input signal (SIN) and a feedback signal (SFB). A feedback path is coupled to the first node to provide the feedback signal, which is either applied to an input of the hysteretic comparator module via a loop filter (701) in the feedback path or applied to the feedforward path prior to a loop filter (701) upstream of the hysteretic comparator module (302). The hysteretic comparator module (302) is configured such that any change in state of the time encoded signal at the first node is synchronised to the first clock signal (CLK1).
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公开(公告)号：US10432151B2
公开(公告)日：2019-10-01
申请号：US15988823
申请日：2018-05-24
Inventor： John Paul Lesso , Toru Ido
IPC: H03F3/68 , H04B15/00 , H04R3/02 , H03F1/32 , H03F3/187 , H04R3/04 , H03F1/02 , H03F3/217 , H04R1/10
Abstract: This application relates to methods and apparatus for amplification of audio signals with improved audio performance. An audio driving circuit has an amplifier module in a forward signal path between an input for receiving an input audio signal (SIN) and an output for outputting an audio driving signal (VOUT). A pre-distortion module is operable to apply a first transfer function to the signal in the forward signal path upstream of the amplifier module, wherein the first transfer function comprises a non-linear distortion function based on at least one distortion setting. An error block is arranged to receive a first signal (SFF) derived from the input signal and a second signal (SFB) indicative of the voltage of the audio driving signal and determine a first error signal (ε1) indicative of a difference between the first and second signals. The pre-distortion module is operable to control the distortion setting(s) based on the first error signal.
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Patent Agency Ranking
公开(公告)号：US10257612B2
公开(公告)日：2019-04-09
申请号：US15439401
申请日：2017-02-22
Inventor： John Paul Lesso , John Laurence Melanson
Abstract: This application relates to methods and apparatus for digital microphones. Disclosed is a digital microphone apparatus (300) for outputting a digital output signal (DATA) at a sample rate defined by a received clock signal (CLK). The apparatus includes a band splitter (302) configured to receive a microphone signal (SMD) indicative of an output of a microphone transducer and split said microphone signal into first signal path (SP1) for frequencies in a first band and a second signal path (SP2) for frequencies in a second band, the frequencies of the second band being higher than the frequencies in the first band. A modulation block (304) is configured to operate on the second signal path to down-convert signals in the second signal path from the second frequency band to a lower frequency band.
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公开(公告)号：US10193561B2
公开(公告)日：2019-01-29
申请号：US15384861
申请日：2016-12-20
Inventor： John Paul Lesso
Abstract: This application relates to methods and apparatus for phase locked loops. A phase-and-frequency detector (101) receives a reference clock signal (CKref) and a feedback signal (SFB) and outputs a first adjustment signal (U) that is modulated between respective first and second signal levels to provide control pulses indicating that an increase in frequency required for phase and frequency lock, and a second adjustment signal (D) that is modulated between respective first and second signal levels to provide control pulses indicating that a decrease in frequency required for phase and frequency lock. First and second time-to-digital converters (201-1 and 201-2) receive the first and second adjustment signals respectively and output respective first and second digital signals indicative of the duration of said control pulses. Each time-to-digital converter comprises a controlled-oscillator (401, 801) configured so as to operate at a first frequency when the respective adjustment signal is at the first signal level and operate at a second frequency when the respective adjustment signal is at the second signal level and a counter (403) configured to produce a count value of the number oscillations of the controlled-oscillator in each of a succession of count periods defined by a count clock signal. The first and second digital signals are based on the count values output from the respective counters. The difference between the first and second digital signals may be determined and input to digital loop filter (203) before driving numerically-controlled-oscillator (204) to produce the output signal.
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公开(公告)号：US10149050B2
公开(公告)日：2018-12-04
申请号：US15315845
申请日：2015-06-04
Inventor： John Paul Lesso
Abstract: This application relates to methods and apparatus for determining the temperature of a voice coil of a loudspeaker (204), for instance as part of a system (208) for protecting the loudspeaker from overheating. The method comprises driving the voice coil with signal components at first and second frequencies, wherein the first frequency (fH) is higher than the second frequency (fL), and determining first and second indications of current (ICM) and voltage (VCM) of the voice coil at said first and second frequencies respectively. The method involves determining an estimated ratio value using the first and second indications of current and voltage, wherein said estimated ratio value corresponds to a ratio between a value based on the resistance of the voice coil and a value based on the inductance of the voice coil. The temperature of the voice coil is then determined based on said estimated ratio value and at least one reference value. An impedance extraction module (210) may extract values for the impedance at the first and second frequencies respectively (ZH, ZL). In some embodiments a module (212) may determine estimated values of the resistance (REM) and inductance (LEM) of the voice coil which are used by temperature estimation block (214) to determine the temperature.
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29.发明申请公开(公告)号：US20180160235A1
公开(公告)日：2018-06-07
申请号：US15830358
申请日：2017-12-04
Inventor： John Paul Lesso , Cedric Andrieu , Calum Cuthill
CPC classification number: H04R23/00 , G01S7/52004 , G01S7/524 , G01S15/10 , H03G3/005 , H03G3/20 , H04B1/04 , H04B11/00 , H04R3/04 , H04R2420/01 , H04R2499/11
Abstract: Driver circuitry is disclosed for driving an electroacoustic transducer to provide an output comprising both ultrasonic and audio signal components. The driver circuitry comprises an adjustment module configured to reduce the level of said ultrasonic component signal in response to an increase in an operational variable indicative of a level of said audio signal component, while also increasing the pulse duration, duty cycle, repetition frequency or frequency span or bandwidth of the ultrasonic component.
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公开(公告)号：US09923574B2
公开(公告)日：2018-03-20
申请号：US15663411
申请日：2017-07-28
Inventor： John Paul Lesso , Emmanuel Philippe Christian Hardy
CPC classification number: H03M7/30 , H03K7/08 , H03K9/08 , H03M1/18 , H03M1/181 , H03M1/50 , H03M1/504 , H03M3/484 , H03M2201/00
Abstract: This application relates to analog-to-digital converters (ADCs). An ADC 200 has a first converter (201) for receiving an analog input signal (AIN) and outputting a time encode signal (DT), such as a pulse-width-modulated (PWM) signal, based on input signal and a first conversion gain setting (GIN). In some embodiments the first converter has a PWM modulator (401) for generating a PWM signal such that the input signal is encoded by pulse widths that can vary continuously in time. A second converter (202) receives the time encoded signal and outputs a digital output signal (DOUT) based on the time encoded signal (DT) and a second conversion gain setting (GO). The second converter may have a first PWM-to-digital modulator (403). A gain allocation block (204) generates the first and second conversion gain settings based on the time encoded signal (DT). The gain allocation block (204) may have a second PWM-to-digital modulator (203) which may be of lower latency and/or lower resolution that the first PWM-to-digital modulator (403).
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