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31 条记录 (耗时 0.036 秒)

    Serial sequencing of automatic program disturb erase verify during a fast erase mode
    22.
    发明授权
    Serial sequencing of automatic program disturb erase verify during a fast erase mode 有权
    在快速擦除模式期间自动程序干扰擦除的串行排序校验

    公开(公告)号：US06370065B1

    公开(公告)日：2002-04-09

    申请号：US09667347

    申请日：2000-09-22

    申请人： Feng Pan ,  Colin Bill

    发明人： Feng Pan ,  Colin Bill

    IPC分类号： G11C1604

    CPC分类号： G11C16/3445 ,  G11C16/344

    摘要： A method for serial sequencing the automatic disturb erase verify (APDEV) function during a multiple sector fast erase mode. The fast erase mode allows a memory device to erase several sectors of memory cells simultaneously. In order to minimize the time required to complete the APDEV and APDE functions, latches store for the address lines of the sector column positions. The APDEV function, therefore, can be performed serially on each of the sectors in the multiple sector group instead of all the sectors in the group simultaneously, thereby decreasing the amount of time required for the APDEV and APDE functions during the fast erase mode.

    摘要翻译： 一种在多扇区快速擦除模式下对自动干扰擦除验证（APDEV）功能进行串行排序的方法。 快速擦除模式允许存储器件同时擦除存储器单元的多个扇区。 为了最小化完成APDEV和APDE功能所需的时间，锁存器存储扇区列位置的地址线。 因此，APDEV功能可以在多个扇区组中的每个扇区上而不是组中的所有扇区同时执行，从而减少快速擦除模式期间APDEV和APDE功能所需的时间量。

    Memory erase management system
    23.
    发明授权
    Memory erase management system 有权
    内存擦除管理系统

    公开(公告)号：US07443712B2

    公开(公告)日：2008-10-28

    申请号：US11470958

    申请日：2006-09-07

    申请人： Colin Bill ,  Mark McClain ,  Michael VanBuskirk

    发明人： Colin Bill ,  Mark McClain ,  Michael VanBuskirk

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0097 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/79

    摘要： A memory erase management system is provided, including providing a resistive change memory cell, coupling a first line to the resistive change memory cell, coupling a line buffer to the first line, providing a charge storage device coupled to the line buffer, and performing a single pulse erase of the resistive change memory cell by discharging a current from the charge storage device through the resistive change memory cell.

    摘要翻译： 提供了一种存储器擦除管理系统，包括提供电阻变化存储单元，将第一行耦合到电阻变化存储单元，将行缓冲器耦合到第一行，提供耦合到行缓冲器的电荷存储装置，以及执行 通过从电荷存储装置通过电阻变化存储单元放电电流来对电阻变化存储单元进行单次脉冲擦除。

    Generation of margining voltage on-chip during testing CAM portion of flash memory device
    24.
    发明授权
    Generation of margining voltage on-chip during testing CAM portion of flash memory device 失效
    在闪速存储器件的测试CAM部分期间片上产生裕度电压

    公开(公告)号：US06707718B1

    公开(公告)日：2004-03-16

    申请号：US10200539

    申请日：2002-07-22

    申请人： Azrul Halim ,  Colin Bill ,  Ken Cheong Cheah ,  Syahrizal Salleh

    发明人： Azrul Halim ,  Colin Bill ,  Ken Cheong Cheah ,  Syahrizal Salleh

    IPC分类号： G11C1606

    CPC分类号： G11C29/44 ,  G11C16/04 ,  G11C29/16 ,  G11C29/48

    摘要： For generating a margining voltage for biasing a gate of a CAM (content addressable memory) cell of a flash memory device fabricated on a semiconductor wafer, a high voltage source is provided with a voltage generator fabricated on the semiconductor wafer. A low voltage source is provided from a node coupled to the voltage generator fabricated on the semiconductor wafer. For example, the voltage generator for providing the high voltage source includes a voltage regulator and a charge pump fabricated on the semiconductor wafer, and the low voltage source is the ground node. In addition, a first transistor is coupled to the high voltage source, and a second transistor is coupled to the low voltage source. A first resistor is coupled between the first transistor and an output node, and a second resistor coupled between the second transistor and the output node. The margining voltage is generated at the output node. The first resistor and the second resistor form a resistive voltage divider at the output node between the high voltage source and the low voltage source when the first transistor and the second transistor are turned on. A logic circuit turns on the first transistor and the second transistor when a first set of control signals indicate that program margining of the CAM cell during a BIST (built-in-self-test) mode is invoked. The first transistor, the second transistor, the first resistor, the second resistor, and the logic circuit are fabricated on the semiconductor wafer. In another embodiment of the present invention, the logic circuit turns off the first transistor and turns on the second transistor such that the output node discharges to a voltage of the low voltage source for erase margining of the CAM cell.

    摘要翻译： 为了产生用于偏置制造在半导体晶片上的闪存器件的CAM（内容可寻址存储器）单元的栅极的裕度电压，高电压源设置有制造在半导体晶片上的电压发生器。 从耦合到制造在半导体晶片上的电压发生器的节点提供低电压源。 例如，用于提供高电压源的电压发生器包括在半导体晶片上制造的电压调节器和电荷泵，而低电压源是接地节点。 此外，第一晶体管耦合到高电压源，第二晶体管耦合到低电压源。 第一电阻器耦合在第一晶体管和输出节点之间，第二电阻耦合在第二晶体管和输出节点之间。 在输出节点产生裕度电压。 当第一晶体管和第二晶体管导通时，第一电阻器和第二电阻器在高电压源和低电压源之间的输出节点处形成电阻分压器。 当第一组控制信号指示在BIST（内置自测试）模式期间CAM单元的编程余量被调用时，逻辑电路接通第一晶体管和第二晶体管。 在半导体晶片上制造第一晶体管，第二晶体管，第一电阻器，第二电阻器和逻辑电路。 在本发明的另一个实施例中，逻辑电路关闭第一晶体管并导通第二晶体管，使得输出节点放电到低电压源的电压以消除CAM单元的擦除裕度。

    On-chip repair of defective address of core flash memory cells
    25.
    发明授权
    On-chip repair of defective address of core flash memory cells 有权
    核心闪存单元故障地址的片上修复

    公开(公告)号：US06631086B1

    公开(公告)日：2003-10-07

    申请号：US10200544

    申请日：2002-07-22

    申请人： Colin Bill ,  Ken Cheong Cheah ,  Edward V. Bautista, Jr. ,  Azrul Halim ,  Darlene G. Hamilton

    发明人： Colin Bill ,  Ken Cheong Cheah ,  Edward V. Bautista, Jr. ,  Azrul Halim ,  Darlene G. Hamilton

    IPC分类号： G11C1606

    CPC分类号： G11C29/72 ,  G11C15/00 ,  G11C16/04 ,  G11C29/16 ,  G11C29/44 ,  G11C29/48

    摘要： In a method and system for repairing defective flash memory cells fabricated on a semiconductor substrate, a repair controller and a plurality of voltage sources are fabricated on the semiconductor substrate. The repair controller controls the voltage sources to apply programming voltages on respective CAM (content addressable memory) flash memory cells in a JUICE state for replacing the defective flash memory cells with a corresponding redundancy element of flash memory cells. In addition, a FAILREP logic is fabricated on the semiconductor substrate for entering a HANG state if no redundancy element of flash memory cells is available or if the defective flash memory cells have been previously repaired.

    摘要翻译： 在用于修复在半导体衬底上制造的有缺陷的闪速存储器单元的方法和系统中，在半导体衬底上制造修复控制器和多个电压源。 修理控制器控制电压源以将编程电压施加在JUICE状态的相应CAM（内容可寻址存储器）闪存单元上，以用闪存单元的相应冗余元件代替有缺陷的闪存单元。 此外，如果没有闪存单元的冗余元件可用或者有缺陷的闪速存储器单元已经被修复，则在半导体衬底上制造FAILREP逻辑用于进入HANG状态。

    Circuit implementation to quench bit line leakage current in programming and over-erase correction modes in flash EEPROM
    26.
    发明授权
    Circuit implementation to quench bit line leakage current in programming and over-erase correction modes in flash EEPROM 有权
    电路实现在闪存EEPROM中编程和过擦除校正模式中的位线漏电流

    公开(公告)号：US6046932A

    公开(公告)日：2000-04-04

    申请号：US417273

    申请日：1999-10-13

    申请人： Colin Bill ,  Sameer S. Haddad ,  Jonathan Shi-Chang Su ,  Vei-Han Chan

    发明人： Colin Bill ,  Sameer S. Haddad ,  Jonathan Shi-Chang Su ,  Vei-Han Chan

    IPC分类号： G11C16/06 ,  G11C16/02 ,  G11C16/30 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  G11C16/12 ,  G11C16/16

    CPC分类号： G11C16/3409 ,  G11C16/30 ,  G11C16/3404

    摘要： A method of and a flash memory device for quenching bitline leakage current during programming and over-erase correction operations. The flash memory cells are organized in an array of I/O blocks with each block having columns and rows. An array of resistors is connected between the common array source connection and ground. The array of resistors is made up of sets of resistors, each set having a programming mode resistor and an APDE mode resistor. A data buffer switches either a programming mode resistor or APDE mode resistor into the circuit when a bitline is selected for either programming or APDE. The values of the resistors are selected to raise the voltage at the source above a selected threshold voltage of the memory cells so that over-erased cells will not provide leakage current to the bitline during either programming or APDE.

    摘要翻译： 一种用于在编程和过擦除校正操作期间淬灭位线泄漏电流的闪存器件的方法和闪存器件。 闪存单元被组织成具有每个块具有列和行的I / O块的阵列。 公共阵列源连接和地之间连接一组电阻。 电阻器阵列由电阻器组成，每组具有编程模式电阻器和APDE模式电阻器。 当选择编程或APDE的位线时，数据缓冲区将编程模式电阻器或APDE模式电阻器切换到电路中。 选择电阻器的值以将源极处的电压提高到存储器单元的选定阈值电压以上，使得在编程或APDE期间，过擦除的单元将不会向位线提供泄漏电流。

    Bit line discharge method for reading a multiple bits-per-cell flash EEPROM
    27.
    发明授权
    Bit line discharge method for reading a multiple bits-per-cell flash EEPROM 失效
    用于读取多个比特单元的闪存EEPROM的位线放电方法

    公开(公告)号：US5754475A

    公开(公告)日：1998-05-19

    申请号：US884547

    申请日：1997-06-27

    申请人： Colin Bill ,  Ravi Gutala ,  Qimeng (Derek) Zhou ,  Jonathan Su

    发明人： Colin Bill ,  Ravi Gutala ,  Qimeng (Derek) Zhou ,  Jonathan Su

    IPC分类号： G11C11/56 ,  G11C11/34

    CPC分类号： G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2211/5622 ,  G11C2211/5634 ,  G11C2211/5642

    摘要： An improved reading structure (110) for performing a read operation in an array of multiple bits-per-cell flash EEPROM memory cells is provided. A memory core array (12) includes a plurality of memory cells, each being previously programmed to one of a plurality of memory conditions defined by memory core threshold voltages. A reference cell array (22) includes a plurality of reference core cells which are selected together with a selected core cell and provides selectively one of a plurality of reference cell bit line voltages defined by reference cell threshold voltages. Each of the reference cells are previously programmed at the same time as when the memory core cells are being programmed. A precharge circuit (36) is used to precharge the array bit lines and the reference bit lines to a predetermined potential. A detector circuit (28) is responsive to the bit line voltages of the reference cells for generating strobe signals. A reading circuit (26) is responsive to the strobe signals for comparing the memory core threshold voltage with each of the reference cell threshold voltages.

    摘要翻译： 提供了一种改进的读取结构（110），用于以多个比特单元的闪存EEPROM存储单元的阵列执行读取操作。 存储器核心阵列（12）包括多个存储器单元，每个存储器单元预先被编程为由存储器核心阈值电压定义的多个存储器条件中的一个。 参考单元阵列（22）包括与选定的核心单元一起选择的多个参考核心单元，并且选择性地提供由参考单元阈值电压限定的多个参考单元位线电压中的一个。 每个参考单元在与存储器核心单元被编程的同时被预先编程。 预充电电路（36）用于将阵列位线和参考位线预充电至预定电位。 检测器电路（28）响应于参考单元的位线电压以产生选通信号。 读取电路（26）响应于选通信号，用于将存储器核心阈值电压与每个参考单元阈值电压进行比较。

    Temperature compensation of thin film diode voltage threshold in memory sensing circuit
    29.
    发明申请
    Temperature compensation of thin film diode voltage threshold in memory sensing circuit 有权

    公开(公告)号：US20060215439A1

    公开(公告)日：2006-09-28

    申请号：US11086884

    申请日：2005-03-22

    申请人： Colin Bill ,  Wei Cai

    发明人： Colin Bill ,  Wei Cai

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0016 ,  B82Y10/00 ,  G11C7/04 ,  G11C11/5664 ,  G11C13/00 ,  G11C13/0014 ,  G11C2213/72 ,  Y10S977/943

    摘要： Systems and methodologies are provided for temperature compensation of thin film diode voltage levels in memory sensing circuits. The subject invention includes a temperature sensitive bias circuit and an array core with a temperature variable select device. The array core can consist of a thin film diode in series with a nanoscale resistive memory cell. The temperature sensitive bias circuit can include a thin film diode in series with two resistors, and provides a temperature compensating bias voltage to the array core. The thin film diode of the temperature sensitive bias circuit tracks the diode of the array core, while the two resistors create a resistive ratio to mimic the effect of temperature and/or process variation(s) on the array core. The compensating bias reference voltage is generated by the temperature sensitive bias circuit, duplicated by a differential amplifier, and utilized to maintain a constant operation voltage level on the nanoscale resistive memory cell.