-
公开(公告)号：US20160371227A1
公开(公告)日：2016-12-22
申请号：US15190608
申请日：2016-06-23
Applicant: D-Wave Systems Inc.
Inventor： William G. Macready , Geordie Rose , Thomas F.W. Mahon , Peter Love , Marshall Drew-Brook
CPC classification number: G06F17/505 , B82Y10/00 , G06F17/11 , G06N99/002
Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a Boolean logic circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A quantum processor may include multiple sets of qubits, each set coupled to respective annealing signal lines such that dynamic evolution of each set of qubits is controlled independently from the dynamic evolutions of the other sets of qubits.
Abstract translation: 解决计算问题可能包括生成计算问题的逻辑电路表示，将逻辑电路表示编码为离散优化问题，以及使用量子处理器来解决离散优化问题。 可以钳位逻辑电路表示的输出，使得解决方案涉及有效执行逻辑电路表示，以确定对应于被钳位的输出的输入。 该表示可以是布尔逻辑电路。 离散优化问题可以由一组微型优化问题组成，其中每个微型优化问题从逻辑电路表示编码相应的逻辑门。 量子处理器可以包括多组量子位，每组量子位耦合到相应的退火信号线，使得每组量子位的动态演化独立于其他量子位集合的动态演化被控制。
-
22.发明授权公开(公告)号：US09490296B2
公开(公告)日：2016-11-08
申请号：US14589574
申请日：2015-01-05
Applicant: D-Wave Systems Inc.
Inventor： Eric Ladizinsky , Geordie Rose , Jeremy P. Hilton , Eugene Dantsker , Byong Hyop Oh
CPC classification number: H01L27/18 , B82Y10/00 , G06N99/002 , H01L28/24 , H01L39/025 , H01L39/223 , H01L39/2406 , H01L39/2493 , Y10S977/707 , Y10S977/723 , Y10S977/943
Abstract: Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap connector.
Abstract translation: 各种技术和设备允许制造超导电路和结构，例如约瑟夫逊结，其可以例如在量子计算机中有用。 例如，可以制造具有插入在能够超导的两个元件或层之间的电介质结构或层的低磁通量噪声三层结构。 超导通孔可以直接覆盖约瑟夫逊结。 诸如约瑟夫逊结的结构可以承载在平坦化的电介质层上。 可以使用翅片来除去结构中的热量。 能够超导的通孔可以具有小于约1微米的宽度。 该结构可以例如通过通孔和/或带连接器耦合到电阻器。
-
公开(公告)号：US20140245249A1
公开(公告)日：2014-08-28
申请号：US14186895
申请日：2014-02-21
Applicant: D-Wave Systems Inc.
Inventor： William Macready , Geordie Rose , Thomas Mahon , Peter Love , Marshall Drew-Brook
IPC: G06F17/50
CPC classification number: G06F17/505 , B82Y10/00 , G06F17/11 , G06N99/002
Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a Boolean logic circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A quantum processor may include multiple sets of qubits, each set coupled to respective annealing signal lines such that dynamic evolution of each set of qubits is controlled independently from the dynamic evolutions of the other sets of qubits.
Abstract translation: 解决计算问题可能包括生成计算问题的逻辑电路表示，将逻辑电路表示编码为离散优化问题，以及使用量子处理器求解离散优化问题。 可以钳位逻辑电路表示的输出，使得解决方案涉及有效地执行逻辑电路表示，以确定对应于被钳位的输出的输入。 该表示可以是布尔逻辑电路。 离散优化问题可以由一组微型优化问题组成，其中每个微型优化问题从逻辑电路表示编码相应的逻辑门。 量子处理器可以包括多组量子位，每组量子位耦合到相应的退火信号线，使得每组量子位的动态演化独立于其他量子位集合的动态演化被控制。
-
公开(公告)号：US20130144925A1
公开(公告)日：2013-06-06
申请号：US13678266
申请日：2012-11-15
Applicant: D-Wave Systems Inc.
Inventor： William Macready , Geordie Rose , Thomas Mahon , Peter Love , Marshall Drew-Brook
IPC: G06F17/10
CPC classification number: G06F17/10 , B82Y10/00 , G06F17/11 , G06N99/002
Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a multiplication circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A multiplication circuit may employ binary representations of factors, and these binary representations may be decomposed to reduce the total number of variables required to represent the multiplication circuit.
Abstract translation: 解决计算问题可能包括生成计算问题的逻辑电路表示，将逻辑电路表示编码为离散优化问题，以及使用量子处理器来解决离散优化问题。 可以钳位逻辑电路表示的输出，使得解决方案涉及有效地执行逻辑电路表示，以确定对应于被钳位的输出的输入。 该表示可以是乘法电路。 离散优化问题可以由一组微型优化问题组成，其中每个微型优化问题从逻辑电路表示编码相应的逻辑门。 乘法电路可以采用因子的二进制表示，并且这些二进制表示可以被分解以减少表示乘法电路所需的变量的总数。
-
公开(公告)号：US11501195B2
公开(公告)日：2022-11-15
申请号：US15641030
申请日：2017-07-03
Applicant: D-WAVE SYSTEMS INC.
Inventor： Geordie Rose , Suzanne Gildert , William G. Macready , Dominic Christoph Walliman
Abstract: Systems, methods and aspects, and embodiments thereof relate to unsupervised or semi-supervised features learning using a quantum processor. To achieve unsupervised or semi-supervised features learning, the quantum processor is programmed to achieve Hierarchal Deep Learning (referred to as HDL) over one or more data sets. Systems and methods search for, parse, and detect maximally repeating patterns in one or more data sets or across data or data sets. Embodiments and aspects regard using sparse coding to detect maximally repeating patterns in or across data. Examples of sparse coding include L0 and L1 sparse coding. Some implementations may involve appending, incorporating or attaching labels to dictionary elements, or constituent elements of one or more dictionaries. There may be a logical association between label and the element labeled such that the process of unsupervised or semi-supervised feature learning spans both the elements and the incorporated, attached or appended label.
-
Patent Agency Ranking
公开(公告)号：US20210342289A1
公开(公告)日：2021-11-04
申请号：US17355458
申请日：2021-06-23
Applicant: D-WAVE SYSTEMS INC.
Inventor： Alexander Maassen van den Brink , Peter Love , Mohammad H.S. Amin , Geordie Rose , David Grant , Miles F.H. Steininger , Paul I. Bunyk , Andrew J. Berkley
Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.
-
公开(公告)号：US11093440B2
公开(公告)日：2021-08-17
申请号：US16859672
申请日：2020-04-27
Applicant: D-WAVE SYSTEMS INC.
Inventor： Alexander Maassen van den Brink , Peter Love , Mohammad H. S. Amin , Geordie Rose , David Grant , Miles F. H. Steininger , Paul I. Bunyk , Andrew J. Berkley
Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.
-
公开(公告)号：US10991755B2
公开(公告)日：2021-04-27
申请号：US16569221
申请日：2019-09-12
Applicant: D-WAVE SYSTEMS INC.
Inventor： Eric Ladizinsky , Geordie Rose , Jeremy P. Hilton , Eugene Dantsker , Byong Hyop Oh
Abstract: Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap connector.
-
公开(公告)号：US10346349B2
公开(公告)日：2019-07-09
申请号：US16173846
申请日：2018-10-29
Applicant: D-WAVE SYSTEMS INC.
Inventor： Alexander Maassen van den Brink , Peter Love , Mohammad H. S. Amin , Geordie Rose , David Grant , Miles F. H. Steininger , Paul I. Bunyk , Andrew J. Berkley
Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.
-
公开(公告)号：US20180308896A1
公开(公告)日：2018-10-25
申请号：US15956404
申请日：2018-04-18
Applicant: D-Wave Systems Inc.
Inventor： Eric Ladizinsky , Geordie Rose , Jeremy P. Hilton , Eugene Dantsker , Byong Hyop Oh
CPC classification number: H01L27/18 , B82Y10/00 , G06N10/00 , H01L28/24 , H01L39/025 , H01L39/223 , H01L39/2406 , H01L39/2493 , Y10S977/707 , Y10S977/723 , Y10S977/943
Abstract: Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap connector.
-
-
-
-
-
-
-
-
-
Search Results
42
records
(took 0.028 seconds)
