中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

42 records (took 0.021 seconds)

    Micro-personal digital assistant including a temperature managed CPU
    22.
    发明授权
    Micro-personal digital assistant including a temperature managed CPU 失效
    微型个人数字助理，包括温度管理CPU

    公开(公告)号：US5721837A

    公开(公告)日：1998-02-24

    申请号：US756049

    申请日：1996-10-15

    Applicant: Dan Kikinis ,  Pascal Dornier ,  William J. Seiler

    Inventor： Dan Kikinis ,  Pascal Dornier ,  William J. Seiler

    IPC: G06F1/16 ,  G06F1/20 ,  G06F3/033 ,  G06F3/048 ,  G06F13/40 ,  G06F21/00 ,  H04M1/247 ,  H04M1/725 ,  H04M3/42 ,  H04M11/06 ,  H04N1/00 ,  H04N1/195 ,  G06F13/00 ,  G06F1/10

    CPC classification number: H04N1/00411 ,  G06F1/1616 ,  G06F1/1626 ,  G06F1/1632 ,  G06F1/203 ,  G06F1/206 ,  G06F13/409 ,  G06F21/62 ,  G06F3/0482 ,  H04M11/06 ,  H04M3/42314 ,  H04N1/00127 ,  H04N1/00236 ,  H04N1/00241 ,  H04N1/00326 ,  H04M1/725 ,  H04M3/42323 ,  H04N1/195 ,  H04N2201/0049 ,  H04N2201/0051 ,  H04N2201/0053 ,  H04N2201/0063 ,  Y02B60/1228 ,  Y02B60/1235 ,  Y02B60/1275

    Abstract: A personal digital assistant module with a local CPU, memory, and I/O interface has a host interface comprising a bus connected to the local CPU and a connector at a surface of the personal digital assistant for interfacing to a bus connector of a host general-purpose computer, providing direct bus communication between the personal digital assistant and the host general-purpose computer. In an embodiment, the personal digital assistant also stores a security code. The personal digital assistant according to the invention forms a host/satellite combination with a host computer having a docking bay, wherein upon docking a docking protocol controls access by the host to memory of the personal digital assistant based on one or more passwords provided by a user to the host. In another embodiment the personal digital assistant also has an expansion port connected to the local CPU, and expansion peripheral devices may be connected and operated through the expansion port. In another embodiment the local CPU has temperature sensing circuitry incorporated in at least one portion of the IC comprising the CPU, clock adjustment circuitry connected to the at least one portion, and control circuitry connected to the temperature sensor and to the clock adjustment circuitry, the control circuitry configured for driving the clock adjustment circuitry to provide an operational clock rate as a function of a temperature indication provided by the temperature sensor.

    Abstract translation: 具有本地CPU，存储器和I / O接口的个人数字助理模块具有包括连接到本地CPU的总线的主机接口和个人数字助理的表面处的连接器，用于与主机总线的总线连接器 提供个人数字助理和主机通用计算机之间的直接总线通信。 在一个实施例中，个人数字助理还存储安全码。 根据本发明的个人数字助理与具有对接间隔的主计算机形成主机/卫星组合，其中在对接时，对接协议基于由个人数字助理提供的一个或多个密码来控制主机对个人数字助理的存储器的访问 用户到主机。 在另一个实施例中，个人数字助理还具有连接到本地CPU的扩展端口，并且扩展外围设备可以通过扩展端口连接和操作。 在另一个实施例中，本地CPU具有并入IC的至少一部分的温度感测电路，其包括CPU，连接到至少一个部分的时钟调整电路以及连接到温度传感器和时钟调整电路的控制电路， 控制电路被配置为驱动时钟调整电路，以提供作为由温度传感器提供的温度指示的函数的操作时钟速率。

    Peripheral device control through integrated drive electronics
    28.
    发明授权
    Peripheral device control through integrated drive electronics 失效
    通过集成驱动电子设备进行外围设备控制

    公开(公告)号：US5964848A

    公开(公告)日：1999-10-12

    申请号：US90509

    申请日：1998-06-04

    Applicant: Dan Kikinis ,  Pascal Dornier

    Inventor： Dan Kikinis ,  Pascal Dornier

    IPC: G06F3/06 ,  G06F13/42 ,  G06F15/04

    CPC classification number: G06F3/0601 ,  G06F13/4226 ,  G06F3/0607 ,  G06F3/0661 ,  G06F3/0674 ,  G06F3/0682 ,  G06F2003/0692

    Abstract: An IDE interface communicates with peripheral devices not conforming to ST506 specification by providing firmware to microcontrollers mounted on the non-conforming peripheral devices to translate between the data structure of an ST506 specification device and the data structure of the non-conforming device. CD-ROM and cartridge tape drive communication is provided. An enhanced IDE interface communicates with multiple peripheral devices by adding a selective ability to the firmware of the conventional IDE interface.

    Abstract translation: IDE接口与不符合ST506规范的外围设备通信，将固件提供给安装在不合格外围设备上的微控制器，以便在ST506规范设备的数据结构与不合格设备的数据结构之间进行转换。 提供CD-ROM和盒式磁带驱动器通信。 增强的IDE接口通过向常规IDE接口的固件添加选择性能力与多个外围设备进行通信。

    Structure and method for mapping interrupt requests in a high-speed CPU interconnect bus system
    29.
    发明授权
    Structure and method for mapping interrupt requests in a high-speed CPU interconnect bus system 失效
    在高速CPU互联总线系统中映射中断请求的结构和方法

    公开(公告)号：US5805901A

    公开(公告)日：1998-09-08

    申请号：US753254

    申请日：1996-11-12

    Applicant: Pascal Dornier ,  Dan Kikinis

    Inventor： Pascal Dornier ,  Dan Kikinis

    IPC: F02B75/02 ,  G06F13/24 ,  G06F13/42 ,  G06F13/38

    CPC classification number: G06F13/24 ,  G06F13/423 ,  F02B2075/027 ,  Y02B60/1228 ,  Y02B60/1235

    Abstract: A compressed I/O bus system for a general-purpose computer multiplexes 32 bit data and addresses on 32 of 42 dedicated parallel signal paths, and optimizes the bus structure by mapping bus requests made by peripheral devices to "high" memory portions of system RAM not dedicated to other purposes. In one aspect a bus controller is programmable to select translation routines stored in system RAM allowing various models and types of CPUs to be supported. Supported CPUs are interchangeable in the system. In another aspect a default interface attached to the compressed I/O bus of the invention, and translates bus states between the optimized compressed bus and one of an ISA bus or an EISA bus.

    Abstract translation: 用于通用计算机的压缩I / O总线系统在42个专用并行信号路径中的32个多路复用32位数据和地址，并且通过将由外围设备产生的总线请求映射到系统RAM的“高”存储器部分来优化总线结构 不致力于其他目的。 在一个方面，总线控制器是可编程的，以选择存储在系统RAM中的转换程序，允许支持各种型号和类型的CPU。 支持的CPU在系统中是可互换的。 在另一方面，附加到本发明的压缩I / O总线的默认接口，并且将优化的压缩总线和ISA总线或EISA总线之一之间的总线状态转换。

Patent Agency Ranking