公开(公告)号：US06909648B2

公开(公告)日：2005-06-21

申请号：US10101241

申请日：2002-03-19

Applicant: Esin Terzioglu ,  Gil I. Winograd

Inventor： Esin Terzioglu ,  Gil I. Winograd

IPC: G11C29/50 ,  G11C7/00

CPC classification number: G11C29/50 ,  G11C11/41 ,  G11C2029/2602

Abstract: A system and method for applying a stress to a hierarchical memory structure in parallel, testing the memory structure for weak defects. The system and method includes writing a logic 0 into all the memory cells in a memory structure. All the high address predecoded lines and alternating predecoded lines for the lowest address are enabled. A voltage drop between neighboring wordlines and bitlines is affected. A logic 1 is written into all the memory cells in the memory structure. An opposite voltage polarity is caused on the bitlines due to the logic 1 in the memory cells. A reverse voltage polarity stress is achieved on the wordlines by flipping the state of the lowest predecoded line (i.e., by changing the input address corresponding to that line.

Abstract translation: 并行应用分层存储器结构的系统和方法，测试弱缺陷的存储器结构。 该系统和方法包括将逻辑0写入存储器结构中的所有存储器单元。 所有高地址预编码线路和最低地址的交替预编码线路都被使能。 相邻字线和位线之间的电压降受到影响。 将逻辑1写入存储器结构中的所有存储单元。 由于存储器单元中的逻辑1，在位线上产生相反的电压极性。 通过翻转最低预编码行的状态（即，通过改变对应于该行的输入地址），在字线上实现反向电压极性应力。

公开(公告)号：US20050111258A1

公开(公告)日：2005-05-26

申请号：US10984077

申请日：2004-11-08

Applicant: Esin Terzioglu ,  Morteza Afghahi ,  Gil Winograd

Inventor： Esin Terzioglu ,  Morteza Afghahi ,  Gil Winograd

IPC: G11C16/04 ,  G11C11/34

CPC classification number: G11C16/0433 ,  G11C2216/10

Abstract: A non-volatile memory cell (10) includes a charge-storing node (16). An electrically insulating first layer (76) is coupled between the node and a source of a first voltage (22). An electrically insulating second layer (66) is coupled between the node and a source of a second voltage (20-21). The area of the first layer is smaller than the area of the second layer. A controller (90) is arranged to cause the first voltage to be greater than the second voltage so that charge is extracted from the node and is arranged to cause the second voltage to be greater than the first voltage so that charge is injected into the node.

Abstract translation: 非易失性存储单元（10）包括电荷存储节点（16）。 电绝缘的第一层（76）耦合在节点和第一电压源（22）之间。 电绝缘的第二层（66）耦合在节点和第二电压源（20-21）之间。 第一层的面积小于第二层的面积。 控制器（90）被布置成使得第一电压大于第二电压，使得从节点提取电荷并且被布置成使得第二电压大于第一电压，使得电荷被注入节点 。

公开(公告)号：US06842379B2

公开(公告)日：2005-01-11

申请号：US10365913

申请日：2003-02-13

Applicant: Zeynep Toros ,  Esin Terzioglu ,  Ahmad O. Siksek ,  Gil I. Winograd ,  Ali Anvar

Inventor： Zeynep Toros ,  Esin Terzioglu ,  Ahmad O. Siksek ,  Gil I. Winograd ,  Ali Anvar

IPC: G11C16/12 ,  G11C16/34

CPC classification number: G11C16/12

Abstract: A digital memory system (30) includes a memory cell (10), a bit line (12), a voltage generator (320) a controller (90) and a charge integrity estimating module (135). A series of successively larger operating voltages are transmitted to the cell from the voltage generator. The controller determines whether a predetermined value has been stored in the cell. The charge integrity estimating module detects the quantity of charge in the memory cell, for example, by using a sense amplifier (170).

Abstract translation: 数字存储器系统（30）包括存储单元（10），位线（12），电压发生器（320），控制器（90）和电荷完整性估计模块（135）。 一系列连续较大的工作电压从电压发生器传输到电池。 控制器确定预定值是否已经存储在单元中。 电荷完整性估计模块例如通过使用读出放大器（170）来检测存储单元中的电荷量。

公开(公告)号：US06724681B2

公开(公告)日：2004-04-20

申请号：US09775476

申请日：2001-02-02

Applicant: Esin Terzioglu ,  Morteza Cyrus Afghahi

Inventor： Esin Terzioglu ,  Morteza Cyrus Afghahi

IPC: G11C800

CPC classification number: G11C7/06

Abstract: A decoder providing asynchronous reset, redundancy, or both an asynchronously-resettable decoder with redundancy. The decoder has a synchronous portion, responsive to a clocked signal; an asynchronous portion coupled with an asynchronous circuit; a feedback-resetting portion, which substantially isolates the synchronous portion from the asynchronous portion coupled with, and interposed between the synchronous portion in response to a asynchronous reset signal; a signal input; a first memory output coupled with a first memory cell group; a second memory output coupled with a second memory cell group; and a selector coupled between the signal input, the first memory output, and the second memory output. This decoder can be memory row-oriented, and thus provide an asynchronously-resettable row decoder with row redundancy, or an asynchronously-resettable column decoder with column redundancy.

Abstract translation: 提供异步复位，冗余或具有冗余的异步可重置解码器的解码器的解码器。 解码器具有响应于时钟信号的同步部分; 与异步电路耦合的异步部分; 反馈复位部分，其响应于异步复位信号，基本上将同步部分与异步部分耦合并插入在同步部分之间; 信号输入; 与第一存储器单元组耦合的第一存储器输出; 与第二存储单元组耦合的第二存储器输出; 以及耦合在信号输入，第一存储器输出和第二存储器输出之间的选择器。 该解码器可以是面向行的存储器，并且因此提供具有行冗余的异步可重置行解码器，或者具有列冗余的异步可重置列解码器。

公开(公告)号：US06492844B2

公开(公告)日：2002-12-10

申请号：US09776220

申请日：2001-02-02

Applicant: Esin Terzioglu ,  Morteza Cyrus Afghahi

Inventor： Esin Terzioglu ,  Morteza Cyrus Afghahi

IPC: G01R1900

CPC classification number: G11C7/06

Abstract: A sense amplifier having a sampling circuit to sample the amplifier input signal; a reference node storing a reference signal corresponding to the input signal; and a timing circuit activating the sampling circuit for a predetermined interval, and admitting the reference signal to the reference node. The sense amplifier also can include a pump capacitor substantially maintaining a value of the reference signal; and a gain circuit coupled with the reference node and disposed to adaptively adjust gain of an output signal produced by the sense amplifier. The sense amplifier can be a single-ended sense amplifier.

Abstract translation: 一种读出放大器，具有对放大器输入信号进行采样的采样电路; 存储与输入信号相对应的参考信号的参考节点; 以及定时电路，以预定间隔激活采样电路，并将参考信号接收到参考节点。 读出放大器还可以包括基本上保持参考信号值的泵电容器; 以及与参考节点耦合并被设置成自适应地调节由读出放大器产生的输出信号的增益的增益电路。 读出放大器可以是单端读出放大器。

公开(公告)号：US08599597B2

公开(公告)日：2013-12-03

申请号：US13465132

申请日：2012-05-07

Applicant: Esin Terzioglu ,  Gregory A. Uvieghara ,  Mehdi H. Sani ,  Anil Kota ,  Sei Seung Yoon

Inventor： Esin Terzioglu ,  Gregory A. Uvieghara ,  Mehdi H. Sani ,  Anil Kota ,  Sei Seung Yoon

IPC: G11C17/00 ,  G11C5/14

CPC classification number: G11C7/24 ,  G11C17/16 ,  G11C17/18

Abstract: In a particular embodiment, an apparatus includes a one-time programmable (OTP) memory circuit configured to be responsive to a programming voltage. The OTP memory circuit includes an OTP memory array including OTP memory cells, a first power switch configured to decouple the OTP memory array from the programming voltage, and a second power switch configured to decouple a subset of the OTP memory cells from the programming voltage.

Abstract translation: 在特定实施例中，装置包括被配置为响应于编程电压的一次可编程（OTP）存储器电路。 OTP存储器电路包括OTP存储器阵列，其包括OTP存储器单元，被配置为将OTP存储器阵列与编程电压分离的第一电源开关和被配置为将OTP存储器单元的子集与编程电压分离的第二电源开关。

公开(公告)号：US20130223176A1

公开(公告)日：2013-08-29

申请号：US13463873

申请日：2012-05-04

Applicant: Esin Terzioglu ,  Changho Jung ,  Shahzad Nazar

Inventor： Esin Terzioglu ,  Changho Jung ,  Shahzad Nazar

IPC: G11C8/10

CPC classification number: G11C8/10

Abstract: Memory pre-decoder circuits employing pulse latch(es) for reducing memory access times, and related systems and methods are disclosed. In one embodiment, the memory pre-decoder circuit includes a memory pre-decoder configured to pre-decode a memory address input within a memory pre-decode setup path to generate a pre-decoded memory address input. Additionally, a pulse latch is provided in the memory pre-decoder circuit outside of the memory pre-decode setup path. The pulse latch samples the pre-decoded memory address input based on a clock signal and generates a pre-decoded memory address output. As such, the memory pre-decode setup path sets up the pre-decoded memory address input prior to the clock signal for the pulse latch. In this manner, the pulse latch is configured to generate a pre-decoded memory address output without increasing setup times in the memory pre-decode setup path.

Abstract translation: 公开了采用用于减少存储器访问时间的脉冲锁存器的存储器预解码器电路以及相关的系统和方法。 在一个实施例中，存储器预解码器电路包括存储器预解码器，其被配置为对在存储器预解码设置路径内输入的存储器地址进行预解码，以产生预解码的存储器地址输入。 此外，在存储器预解码设置路径外部的存储器预解码器电路中提供脉冲锁存器。 脉冲锁存器基于时钟信号对预解码的存储器地址输入进行采样，并产生预解码的存储器地址输出。 因此，存储器预译码设置路径在脉冲锁存器的时钟信号之前建立预先解码的存储器地址输入。 以这种方式，脉冲锁存器被配置为产生预解码的存储器地址输出，而不增加存储器预解码设置路径中的建立时间。

公开(公告)号：US08379478B2

公开(公告)日：2013-02-19

申请号：US13435020

申请日：2012-03-30

Applicant: Ali Anvar ,  Gil I. Winograd ,  Esin Terzioglu

Inventor： Ali Anvar ,  Gil I. Winograd ,  Esin Terzioglu

IPC: G11C8/00

CPC classification number: G11C11/419 ,  G06F13/4086 ,  G11C5/025 ,  G11C5/06 ,  G11C7/06 ,  G11C7/1039 ,  G11C7/1072 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C11/41 ,  G11C11/412 ,  G11C11/413 ,  G11C29/808 ,  G11C29/848

Abstract: The present invention relates to a system and method for adjusting timing of memory access operations to a memory block. In one embodiment, a controller may be in communication with a memory block. The controller may be adapted to adjust timing of a memory access operation to the memory block by extending a portion of a clock pulse to compensate for delay associated with the memory block. The delay may correspond to a predecoder delay or a global decoder delay. The clock pulse may be a read clock pulse or a write clock pulse. In one embodiment, the controller may be adapted to adjust timing of a read clock pulse differently from a write clock pulse.

Abstract translation: 本发明涉及一种用于调整对存储器块的存储器访问操作的定时的系统和方法。 在一个实施例中，控制器可以与存储器块通信。 控制器可以适于通过延长时钟脉冲的一部分来补偿与存储器块相关联的延迟来调整对存储器块的存储器访问操作的定时。 延迟可以对应于预解码器延迟或全局解码器延迟。 时钟脉冲可以是读时钟脉冲或写时钟脉冲。 在一个实施例中，控制器可以适于调整与写入时钟脉冲不同的读取时钟脉冲的定时。

公开(公告)号：US07889553B2

公开(公告)日：2011-02-15

申请号：US12109331

申请日：2008-04-24

Applicant: Esin Terzioglu ,  Gil I. Winograd ,  Morteza Cyrus Afghahi

Inventor： Esin Terzioglu ,  Gil I. Winograd ,  Morteza Cyrus Afghahi

IPC: G11C16/04 ,  H01L29/788

CPC classification number: G11C16/0425 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7883

Abstract: A non-volatile memory cell includes: a substrate including diffusion regions for a read-out transistor; a capacitor formed in a poly-silicon layer adjacent the substrate, the capacitor including a floating gate for the read-out transistor and a control gate, the floating gate and the control gate each having finger extensions, the finger extensions from the floating gate interdigitating with the finger extensions from the control gate; anda programming line coupled to the control gate.

Abstract translation: 非挥发性存储单元包括：包括用于读出晶体管的扩散区域的衬底; 形成在与衬底相邻的多晶硅层中的电容器，所述电容器包括用于读出晶体管的浮置栅极和控制栅极，所述浮置栅极和控制栅极各自具有指状延伸，所述浮动栅极的指状延伸部交叉 手指从控制门延伸; 以及耦合到控制门的编程线。

公开(公告)号：US07719920B2

公开(公告)日：2010-05-18

申请号：US11766200

申请日：2007-06-21

Applicant: Ali Anvar ,  Gil I. Winograd ,  Esin Terzioglu

Inventor： Ali Anvar ,  Gil I. Winograd ,  Esin Terzioglu

IPC: G11C8/00

CPC classification number: G11C11/419 ,  G06F13/4086 ,  G11C5/025 ,  G11C5/06 ,  G11C7/1039 ,  G11C7/1072 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C11/41 ,  G11C11/412 ,  G11C11/413 ,  G11C29/808 ,  G11C29/848 ,  Y02D10/14 ,  Y02D10/151

Abstract: The present invention relates to a system and method for processing the read and write operations in a memory architecture. The system processing the read and write operations includes at least one local memory block and a synchronously controlled global controller coupled to the local memory block and adapted to extend the high portion of a clock pulse. The method for processing the read and write operations includes skewing a clock pulse using at least one word line interfacing with the global controller.

Abstract translation: 本发明涉及用于处理存储器架构中的读写操作的系统和方法。 处理读和写操作的系统包括耦合到本地存储器块并且适于延长时钟脉冲的高部分的至少一个本地存储器块和同步控制的全局控制器。 用于处理读取和写入操作的方法包括使用与全局控制器接口的至少一个字线来扭曲时钟脉冲。