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公开(公告)号：US07439759B2
公开(公告)日：2008-10-21
申请号：US10558145
申请日：2004-05-17
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： G06F13/4072
摘要： As technology scales, on-chip interconnects are becoming narrower, and the height of such interconnects is not scaling linearly with the width. This leads to an increase of coupling capacitance with neighboring wires, leading to higher crosstalk. It also leads to poor performance due to poor RC response at the receiving of the wire, which may even result in failure in very noisy environments. An adaptive threshold scheme is proposed in which receiver switching thresholds are adjusted according to the detected noise in bus lines. These noise levels are dependent on both the front-end processing (transistor performance) as well as on the backend processing (metal resistance, capacitance, width and spacing). The circuit therefore automatically compensates for process variations.
摘要翻译： 随着技术的发展，片上互连变得越来越窄，这种互连的高度并没有随宽度而线性缩放。 这导致与相邻导线的耦合电容的增加，导致更高的串扰。 由于在接收线路时RC响应差，导致性能差，甚至可能导致非常嘈杂的环境中的故障。 提出了一种自适应阈值方案，其中接收机切换阈值根据总线线路中检测到的噪声进行调整。 这些噪声水平取决于前端处理（晶体管性能）以及后端处理（金属电阻，电容，宽度和间距）。 因此，电路自动补偿过程变化。
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公开(公告)号：US20060244488A1
公开(公告)日：2006-11-02
申请号：US10525865
申请日：2003-07-31
申请人： Atul Katoch , Evert Seevinck , Hendricus Veendrick
发明人： Atul Katoch , Evert Seevinck , Hendricus Veendrick
IPC分类号： H03K19/0175
CPC分类号： H04L25/08 , H04L25/026 , H04L25/0272 , H04L25/0294
摘要： An electronic data processing circuit uses current mode signalling on a communication conductor, wherein a receiver supplies current to the communication conductor to try and keep a voltage on the conductor constant and measures the current that is needed to do so. A transition coding circuit is coupled between a data source circuit and the communication conductor, for driving the communication conductor in a first state in pulses in response to transitions in the logic signal and in a second state outside the pulses. The level that is used for indicating no change is selected so the current that needs to be supplied by the receiver is smaller when no change is signalled than when a change is signalled. Preferably only a nearly zero quiescent current is needed when there is no change.
摘要翻译： 电子数据处理电路在通信导体上使用电流模式信号，其中接收器向通信导体提供电流以尝试并保持导体上的电压恒定并且测量所需的电流。 转换编码电路耦合在数据源电路和通信导体之间，用于响应于逻辑信号中的转换和在脉冲之外的第二状态以脉冲方式驱动通信导体处于第一状态。 选择用于指示没有变化的电平，所以当没有发出变化时，接收器需要提供的电流比发出变化时更小。 当没有变化时，最好只需要几乎零静态电流。
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公开(公告)号：US6140664A
公开(公告)日：2000-10-31
申请号：US408088
申请日：1995-03-21
申请人： Evert Seevinck , Tjerk G. Spanjer
发明人： Evert Seevinck , Tjerk G. Spanjer
CPC分类号： H01J1/308 , H01J29/04 , H01J2201/319
摘要： To prevent breakdown of an insulating layer located underneath a gate electrode, the gate electrode is connected to an external terminal via a high-ohmic resistor. The high-ohmic resistor may form part of a resistive network for biasing voltages for a plurality of gate electrodes. The resistive network may be realised partly on the insulating layer.
摘要翻译： 为了防止位于栅电极下方的绝缘层的击穿，栅电极通过高欧姆电阻连接到外部端子。 高欧姆电阻可以形成用于多个栅电极的偏置电压的电阻网络的一部分。 电阻网络可以部分地实现在绝缘层上。
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公开(公告)号：US5329481A
公开(公告)日：1994-07-12
申请号：US989629
申请日：1992-12-14
IPC分类号： H01L21/8247 , G11C11/34 , H01L21/8229 , H01L27/102 , H01L27/115
CPC分类号： G11C11/34
摘要： A semiconductor device with at least one programmable memory cell which includes a bipolar transistor (T.sub.1) with an emitter (11) and a collector (12) of a first conductivity type and a base (10) of a second, opposite conductivity type. The emitter (11) and collector (12) are coupled to a first supply line (100) and a second supply line (200), respectively. The base (10) is coupled to writing means (WRITE) through a control transistor (T.sub.2). Reading means (READ) are included in a current path (I) which extends between the first supply line (100) and the second supply line (200) and which includes a current path between the emitter (11) and collector (12). In a preferred embodiment, the collector (12) is in addition coupled to the second supply line (200) via a switchable load (T.sub.5).
摘要翻译： 一种具有至少一个可编程存储单元的半导体器件，其包括具有第一导电类型的发射极（11）和集电极（12）的双极晶体管（T1）和具有第二导电类型的第二基极（10）。 发射极（11）和集电极（12）分别耦合到第一电源线（100）和第二供电线（200）。 基极（10）通过控制晶体管（T2）耦合到写入装置（WRITE）。 读取装置（READ）包括在第一电源线（100）和第二电源线（200）之间延伸的电流路径（I）中，并且包括发射器（11）和集电极（12）之间的电流路径。 在优选实施例中，收集器（12）还经由可切换负载（T5）耦合到第二供电管线（200）。
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25.发明授权Reference generator for generating a reference voltage and a reference current 失效用于产生参考电压和参考电流的参考发生器
公开(公告)号：US5173656A
公开(公告)日：1992-12-22
申请号：US690446
申请日：1991-04-23
申请人： Evert Seevinck , Philip D. Costello
发明人： Evert Seevinck , Philip D. Costello
IPC分类号： G05F3/26
CPC分类号： G05F3/262 , Y10S323/907
摘要： A reference generator includes a first, a second and an additional third current mirror for generating both a reference output current and a reference output voltage. As the reference output voltage only depends on the gate-source voltages of transistors which are fed with a constant current, the reference output voltage has a constant value and is substantially independent of the ambient temperature.
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公开(公告)号：US5006815A
公开(公告)日：1991-04-09
申请号：US418414
申请日：1989-10-06
CPC分类号： H03F1/3211 , H03G1/04
摘要： A linear-gain amplifier arrangement comprises a current amplifying cell consisting of field-effect transistors and comprising a first (M1, M3) and a second (M2, M4current-mirror circuit whose respective input transistors (M1; M2) and output transistors (M3; M4) constitute a first and a second differential pair. The input transistors (M1; M2) have their drain electrodes connected to voltage-current converter (V/I) made up of field-effect transistors. The V/I converter supplies difference currents (I.sub.in1 ; I.sub.in2) which are square-law functions of the input voltage (U.sub.in) to be amplified. The difference between these input currents is a linear function of the input voltage. When the transistors are operated in their saturation regions the difference between the output currents (I.sub.out1 ; I.sub.out2) is also a linear function of the input voltage (U.sub.in). By adding a direct voltage (V.sub.c) to the gate-source voltage of the input and output transistors or by adding a direct current (I.sub.c) to the respective input currents (I.sub.in1 ; I.sub.in2) the gain can be varied without a change in bandwidth. When the arrangement is constructed as an integrated semiconductor circuit its gain can be made immune to temperature variations and tolerances in the fabrication process.
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公开(公告)号：US20060244481A1
公开(公告)日：2006-11-02
申请号：US10558145
申请日：2004-05-17
申请人： Atul Katoch , Manish Garg , Evert Seevinck , Hendricus Veendrick
发明人： Atul Katoch , Manish Garg , Evert Seevinck , Hendricus Veendrick
IPC分类号： H03K19/003
CPC分类号： G06F13/4072
摘要： As technology scales, on-chip interconnects are becoming narrower, and the height of such interconnects is not scaling linearly with the width. This leads to an increase of coupling capacitance with neighboring wires, leading to higher crosstalk. It also leads to poor performance due to poor RC response at the receiving of the wire, which may even result in failure in very noisy environments. An adaptive threshold scheme is proposed in which receiver switching thresholds are adjusted according to the detected noise in bus lines. These noise levels are dependent on both the front-end processing (transistor performance) as well as on the backend processing (metal resistance, capacitance, width and spacing). The circuit therefore automatically compensates for process variations.
摘要翻译： 随着技术的发展，片上互连变得越来越窄，这种互连的高度并没有随宽度而线性缩放。 这导致与相邻导线的耦合电容的增加，导致更高的串扰。 由于在接收线路时RC响应差，导致性能差，甚至可能导致非常嘈杂的环境中的故障。 提出了一种自适应阈值方案，其中接收机切换阈值根据总线线路中检测到的噪声进行调整。 这些噪声水平取决于前端处理（晶体管性能）以及后端处理（金属电阻，电容，宽度和间距）。 因此，电路自动补偿过程变化。
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公开(公告)号：US07038936B2
公开(公告)日：2006-05-02
申请号：US10503459
申请日：2003-01-20
申请人： Evert Seevinck , Alain Michel Marie Thijs , Patrick Van De Steeg , Maurits Mario Nicolaas Storms
发明人： Evert Seevinck , Alain Michel Marie Thijs , Patrick Van De Steeg , Maurits Mario Nicolaas Storms
IPC分类号： G11C11/00
CPC分类号： G11C7/062 , G11C11/419
摘要： A reading circuit comprises a first and second cascode circuit and a first and second current mirror. The first cascode circuit can be connected to a bit line of a memory cell and the second cascode circuit can be connected to a reference bit line of a reference cell. The first output terminals of the first and second cascode circuits are connected to first terminals of the first and second current mirrors, respectively. The second output terminals of the first and second cascode circuits are connected to the second terminals of the second and first current mirrors, respectively. A tri-state buffer is coupled between the second terminals of the first and second current mirrors said buffer having bit invert capabilities.
摘要翻译： 读取电路包括第一和第二共源共栅电路以及第一和第二电流镜。 第一级联电路可以连接到存储器单元的位线，并且第二级联电路可以连接到参考单元的参考位线。 第一和第二共源共栅电路的第一输出端分别连接到第一和第二电流镜的第一端。 第一和第二共源共栅电路的第二输出端分别连接到第二和第一电流镜的第二端。 三态缓冲器耦合在第一和第二电流镜的第二端之间，所述缓冲器具有位反转能力。
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公开(公告)号：US06489708B1
公开(公告)日：2002-12-03
申请号：US09218548
申请日：1998-12-22
IPC分类号： H01J3100
CPC分类号： H01J29/46 , H01J31/203 , H01J2229/0761 , H01J2231/1255
摘要： A cathode ray tube device in which two deflection yokes and two electron guns are used, but in which only one shadow mask is used. Image uniformity is obtained by creating a partial overlap of the two images created by the two yokes.
摘要翻译： 使用两个偏转轭和两个电子枪的阴极射线管装置，其中仅使用一个荫罩。 通过创建由两个轭创建的两个图像的部分重叠来获得图像均匀性。
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公开(公告)号：US06205070B1
公开(公告)日：2001-03-20
申请号：US09464856
申请日：1999-12-16
IPC分类号： G11C700
CPC分类号： G11C11/419 , G11C7/062
摘要： A memory in an integrated circuit contains a current sense amplifier. The current sense amplifier contains a first and second input transistor with cross-coupled gates and drains, each transistor having a source coupled to a respective memory bit line. The current from the drains of the first and second input transistor is guided to source-drain channels of the first and second load transistor respectively. The drains of the first and second input transistor are coupled to a common node via source-gate links of the first and second load transistor respectively. The gate/source voltage drops of the first and second load transistor are arranged in a direction opposite to a direction of gate/source voltage drops of the first and second input transistor between the complementary bit lines and the common node.
摘要翻译： 集成电路中的存储器包含电流检测放大器。 电流检测放大器包含具有交叉耦合栅极和漏极的第一和第二输入晶体管，每个晶体管具有耦合到相应存储器位线的源极。 来自第一和第二输入晶体管的漏极的电流分别被引导到第一和第二负载晶体管的源极 - 漏极通道。 第一和第二输入晶体管的漏极分别通过第一和第二负载晶体管的源极 - 栅极耦合到公共节点。 第一和第二负载晶体管的栅极/源极电压降沿与互补位线和公共节点之间的第一和第二输入晶体管的栅极/源极电压降的方向相反的方向排列。
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