公开(公告)号：US07821013B2

公开(公告)日：2010-10-26

申请号：US11501777

申请日：2006-08-10

Applicant: Rajesh Kumar ,  Yuichi Takeuchi ,  Mitsuhiro Kataoka ,  Suhail Rashid Jeremy ,  Andrei Mihaila ,  Florin Udrea

Inventor： Rajesh Kumar ,  Yuichi Takeuchi ,  Mitsuhiro Kataoka ,  Suhail Rashid Jeremy ,  Andrei Mihaila ,  Florin Udrea

IPC: H01L29/12 ,  H01L29/41

CPC classification number: H01L29/8083 ,  H01L29/1608

Abstract: A silicon carbide semiconductor device includes: a semiconductor substrate including first and second gate layers, a channel layer, a source layer, and a trench; a gate wiring having a first portion and a plurality of second portions; and a source wiring having a third portion and a plurality of fourth portions. The trench extends in a predetermined extending direction. The first portion connects to the first gate layer in the trench, and extends to the extending direction. The second portions protrude perpendicularly to be a comb shape. The third portion extends to the extending direction. The fourth portions protrude perpendicularly to be a comb shape, and electrically connect to the source layer. Each of the second portions connects to the second gate layer through a contact hole.

Abstract translation: 碳化硅半导体器件包括：包括第一和第二栅极层，沟道层，源极层和沟槽的半导体衬底; 栅极布线，具有第一部分和多个第二部分; 以及具有第三部分和多个第四部分的源极布线。 沟槽沿预定的延伸方向延伸。 第一部分连接到沟槽中的第一栅极层，并延伸到延伸方向。 第二部分垂直突出成为梳形。 第三部分延伸到延伸方向。 第四部分垂直突出成梳状，并且电连接到源层。 每个第二部分通过接触孔连接到第二栅极层。

公开(公告)号：US07679160B2

公开(公告)日：2010-03-16

申请号：US11216197

申请日：2005-09-01

Applicant: Florin Udrea ,  Gehan Anil Joseph Amaratunga

Inventor： Florin Udrea ,  Gehan Anil Joseph Amaratunga

IPC: H01L29/93

CPC classification number: H01L29/86 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0634 ,  H01L29/66325 ,  H01L29/7317 ,  H01L29/7394 ,  H01L29/7824 ,  H01L29/78603 ,  H01L29/868 ,  H02M7/003

Abstract: A high voltage/power semiconductor device has at least one active region having a plurality of high voltage junctions electrically connected in parallel. At least part of each of the high voltage junctions is located in or on a respective membrane such that the active region is provided at least in part over plural membranes. There are non-membrane regions between the membranes. The device has a low voltage terminal and a high voltage terminal. At least a portion of the low voltage terminal and at least a portion of the high voltage terminal are connected directly or indirectly to a respective one of the high voltage junctions. At least those portions of the high voltage terminal that are in direct or indirect contact with one of the high voltage junctions are located on or in a respective one of the plural membranes.

Abstract translation: 高电压/功率半导体器件具有至少一个有源区，其具有并联电连接的多个高电压结。 每个高电压接头的至少一部分位于相应的膜中或上，使得有源区至少部分地设置在多个膜上。 膜之间有非膜区。 该器件具有低电压端子和高压端子。 低电压端子的至少一部分和高电压端子的至少一部分直接或间接地连接到相应的一个高压接点。 至少与高压接点中的一个直接或间接接触的高压端子的那些部分位于多个膜中的相应的一个上或其中。

公开(公告)号：US07531993B2

公开(公告)日：2009-05-12

申请号：US11847234

申请日：2007-08-29

Applicant: Florin Udrea ,  Nishad Udugampola ,  Gehan A. J. Amaratunga

Inventor： Florin Udrea ,  Nishad Udugampola ,  Gehan A. J. Amaratunga

IPC: G05F3/16 ,  H03K3/35

CPC classification number: H03K17/567 ,  H01L29/0638 ,  H01L29/7393 ,  H03K17/08142 ,  H03K17/6871 ,  H03K2017/6878

Abstract: A half bridge circuit has a first switch having at least one control gate and a second switch having at least two control gates. A first driver has an output connected to a control gate of the first switch. A second driver has an output connected to a first control gate of the second switch. The output of the first driver is connected to a second control gate of the second switch by a circuit arrangement such that when the first driver is operated to apply a high, positive voltage to the control gate of the first switch, a positive voltage is applied to the second control gate of the second switch, and such that when the first driver is operated to apply a low, zero or small voltage to the control gate of the first switch, a negative voltage is applied to said second control gate of the second switch.

Abstract translation: 半桥电路具有具有至少一个控制栅极的第一开关和具有至少两个控制栅极的第二开关。 第一驱动器具有连接到第一开关的控制栅极的输出端。 第二驱动器具有连接到第二开关的第一控制栅极的输出。 第一驱动器的输出通过电路装置连接到第二开关的第二控制栅极，使得当第一驱动器被操作以向第一开关的控制栅极施加高正正电压时，施加正电压 并且使得当第一驱动器被操作以向第一开关的控制栅极施加低，零或小电压时，负电压被施加到第二开关的第二控制栅极的第二控制栅极 开关。

公开(公告)号：US07485509B2

公开(公告)日：2009-02-03

申请号：US11594896

申请日：2006-11-09

Applicant: Rajesh Kumar ,  Florin Udrea ,  Andrei Mihaila

Inventor： Rajesh Kumar ,  Florin Udrea ,  Andrei Mihaila

IPC: H01L21/00 ,  H01L21/84

CPC classification number: H01L29/66068 ,  H01L27/0705 ,  H01L27/088 ,  H01L29/1608 ,  H01L29/808 ,  H01L29/8083

Abstract: A semiconductor device includes a first field effect transistor including a source and a gate and disposed in a silicon carbide substrate; and a second field effect transistor including a drain and a gate and disposed in the substrate. The drain of the second field effect transistor connects to the source of the first field effect transistor. The gate of the second field effect transistor connects to the gate of the first field effect transistor.

Abstract translation: 半导体器件包括：第一场效应晶体管，其包括源极和栅极，并设置在碳化硅衬底中; 以及包括漏极和栅极并设置在所述衬底中的第二场效应晶体管。 第二场效应晶体管的漏极连接到第一场效应晶体管的源极。 第二场效应晶体管的栅极连接到第一场效应晶体管的栅极。

公开(公告)号：US07355226B2

公开(公告)日：2008-04-08

申请号：US11414308

申请日：2006-05-01

Applicant: Gehan Anil Joseph Amaratunga ,  Florin Udrea

Inventor： Gehan Anil Joseph Amaratunga ,  Florin Udrea

IPC: H01L29/786

CPC classification number: H01L29/7824 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41725 ,  H01L29/4175 ,  H01L29/42368 ,  H01L29/78603 ,  H01L29/78624

Abstract: This invention is generally concerned with power semiconductors such as power MOS transistors, insulated gate by bipolar transistors (IGBTs), high voltage diodes and the like, and method for their fabrication. A power semiconductor, the semiconductor comprising a power device, said power device having first and second electrical contact regions and a drift region extending therebetween; and a semiconductor substrate mounting said device; and wherein said power semiconductor includes an electrically insulating layer between said semiconductor substrate and said power device, said electrically insulating layer having a thickness of at least 5 μm.

Abstract translation: 本发明通常涉及诸如功率MOS晶体管，双极晶体管（IGBT），高压二极管等的绝缘栅极等功率半导体及其制造方法。 功率半导体，所述半导体包括功率器件，所述功率器件具有第一和第二电接触区域以及在其间延伸的漂移区域; 以及安装所述装置的半导体衬底; 并且其中所述功率半导体在所述半导体衬底和所述功率器件之间包括电绝缘层，所述电绝缘层具有至少5μm的厚度。

公开(公告)号：US20070200117A1

公开(公告)日：2007-08-30

申请号：US11785276

申请日：2007-04-17

Applicant: Rajesh Kumar ,  Andrei Mihaila ,  Florin Udrea

Inventor： Rajesh Kumar ,  Andrei Mihaila ,  Florin Udrea

IPC: H01L31/0312

CPC classification number: H01L29/1608 ,  H01L29/66068 ,  H01L29/8083 ,  Y10S438/931

Abstract: A silicon carbide semiconductor device includes a substrate and a junction field effect transistor. The transistor includes: a first semiconductor layer disposed on the substrate; a first gate layer disposed on a surface of the first semiconductor layer; a first channel layer adjacent to the first gate layer on the substrate; a first source layer connecting to the first channel layer electrically; a second gate layer adjacent to the first channel layer to sandwich the first channel layer; a second channel layer adjacent to the second gate layer to sandwich the second gate layer; a third gate layer adjacent to the second channel layer to sandwich the second channel layer; and a second source layer connecting to the second channel layer electrically.

公开(公告)号：US07235439B2

公开(公告)日：2007-06-26

申请号：US11174606

申请日：2005-07-06

Applicant: Florin Udrea ,  Gehan A J Amaratunga

Inventor： Florin Udrea ,  Gehan A J Amaratunga

IPC: H01L21/8238

CPC classification number: H01L29/7816 ,  H01L21/76289 ,  H01L21/764 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/083 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/42368 ,  H01L29/66325 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7393 ,  H01L29/7394 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7801 ,  H01L29/7802 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/7824 ,  H01L29/7831 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A power semiconductor device has an active region that includes a drift region. At least a portion of the drift region is provided in a membrane which has opposed top and bottom surfaces. In one embodiment, the top surface of the membrane has electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region. In another embodiment, at least one electrical terminal is connected directly or indirectly to the top surface and at least one electrical terminal is connected directly or indirectly to the bottom surface to allow a voltage to be applied vertically across the drift region. In each of these embodiments, the bottom surface of the membrane does not have a semiconductor substrate positioned adjacent thereto.

Abstract translation: 功率半导体器件具有包括漂移区域的有源区域。 漂移区域的至少一部分设置在具有相对的顶表面和底表面的膜中。 在一个实施例中，膜的顶表面具有直接或间接连接到其上的电端子，以允许跨越漂移区横向施加电压。 在另一个实施例中，至少一个电端子直接或间接地连接到顶表面，并且至少一个电端子直接或间接地连接到底表面，以允许垂直地跨越漂移区域施加电压。 在这些实施例的每一个中，膜的底表面不具有与其相邻定位的半导体衬底。

公开(公告)号：US07230275B2

公开(公告)日：2007-06-12

申请号：US10984957

申请日：2004-11-10

Applicant: Rajesh Kumar ,  Andrei Mihaila ,  Florin Udrea

Inventor： Rajesh Kumar ,  Andrei Mihaila ,  Florin Udrea

IPC: H01L29/15

CPC classification number: H01L29/1608 ,  H01L29/66068 ,  H01L29/8083 ,  Y10S438/931

Abstract: A silicon carbide semiconductor device includes a substrate and a junction field effect transistor. The transistor includes: a first semiconductor layer disposed on the substrate; a first gate layer disposed on a surface of the first semiconductor layer; a first channel layer adjacent to the first gate layer on the substrate; a first source layer connecting to the first channel layer electrically; a second gate layer adjacent to the first channel layer to sandwich the first channel layer; a second channel layer adjacent to the second gate layer to sandwich the second gate layer; a third gate layer adjacent to the second channel layer to sandwich the second channel layer; and a second source layer connecting to the second channel layer electrically.

Abstract translation: 碳化硅半导体器件包括衬底和结场效应晶体管。 晶体管包括：设置在基板上的第一半导体层; 设置在所述第一半导体层的表面上的第一栅极层; 与所述基板上的所述第一栅极层相邻的第一沟道层; 电连接到第一沟道层的第一源极层; 与所述第一沟道层相邻以夹住所述第一沟道层的第二栅极层; 与所述第二栅极层相邻以夹住所述第二栅极层的第二沟道层; 与所述第二沟道层相邻以夹住所述第二沟道层的第三栅极层; 以及电连接到第二沟道层的第二源极层。

公开(公告)号：US20060154401A1

公开(公告)日：2006-07-13

申请号：US11092654

申请日：2005-03-30

Applicant: Julian Gardner ,  James Covington ,  Florin Udrea

Inventor： Julian Gardner ,  James Covington ,  Florin Udrea

IPC: H01L21/00

CPC classification number: G01N27/128

Abstract: A gas-sensing semiconductor device is fabricated on a silicon substrate having a thin silicon oxide insulating layer in which a resistive heater made of a CMOS compatible high temperature metal is embedded. The high temperature metal is tungsten. The device includes at least one sensing area provided with a gas-sensitive layer separated from the heater by an insulating layer. As one of the final fabrication steps, the substrate is back-etched so as to form a thin membrane in the sensing area. Except for the back-etch and the gas-sensitive layer formation, that are carried out post-CMOS, all other layers, including the tungsten resistive heater, are made using a CMOS process employing tungsten metallisation. The device can be monolithically integrated with the drive, control and transducing circuitry using low cost CMOS processing. The heater, the insulating layer and other layers are made within the CMOS sequence and they do not require extra masks or processing.

公开(公告)号：US06858884B2

公开(公告)日：2005-02-22

申请号：US10602065

申请日：2003-06-24

Applicant: Florin Udrea

Inventor： Florin Udrea

IPC: H01L29/06 ,  H01L29/739 ,  H01L29/78 ,  H01L29/786 ,  H01L29/861 ,  H01L29/868 ,  H01L29/74 ,  H01L31/111

CPC classification number: H01L29/0634 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0886 ,  H01L29/7394 ,  H01L29/7824 ,  H01L29/861

Abstract: A lateral semiconductor device (10) has a semiconductor layer (15) on an insulating substrate (16). The semiconductor layer (15) has a first region (12) of a first conduction type and a second region (13) of a second conduction type with a drift region (14) therebetween. The drift region (14) is provided by a third region (14″) of the first conduction type and a fourth region (14′) of the second conduction type. The third and fourth (drift) regions (14″,14′) are so arranged that when a reverse voltage bias is applied across the first and second regions (12,13) of the semiconductor layer (15), the third region (14″) has locally in the proximity of the first region (12) an excess of impurity charge relative to the fourth region (14′), and the fourth region (14′) has locally in the proximity of the second region (13) an excess of impurity charge relative to the third region (14″), and the total volume charge in the third region (14″) is substantially equal to the total volume charge in the fourth region (14′).

Abstract translation: 横向半导体器件（10）在绝缘基板（16）上具有半导体层（15）。 半导体层（15）具有第一导电类型的第一区域（12）和第二导电类型的第二区域（13），其间具有漂移区域（14）。 漂移区域（14）由第一导电类型的第三区域（14“）和第二导电类型的第四区域（14'）提供。 第三和第四（漂移）区域（14“，14”）被布置成使得当跨越半导体层（15）的第一和第二区域（12,13）施加反向电压偏压时，第三区域 14“）在第一区域（12）附近具有相对于第四区域（14'）过多的杂质电荷，并且第四区域（14'）局部地位于第二区域（13）附近 ）相对于第三区域（14“）的过量的杂质电荷，并且第三区域（14”）中的总体积电荷基本上等于第四区域（14'）中的总体积电荷。