公开(公告)号：US07411272B2

公开(公告)日：2008-08-12

申请号：US11174605

申请日：2005-07-06

Applicant: Florin Udrea ,  Gehan A. J. Amaratunga

Inventor： Florin Udrea ,  Gehan A. J. Amaratunga

IPC: H01L29/00

CPC classification number: H01L29/7816 ,  H01L21/76289 ,  H01L21/764 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/083 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/42368 ,  H01L29/66325 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7393 ,  H01L29/7394 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7801 ,  H01L29/7802 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/7824 ,  H01L29/7831 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A power semiconductor device has an active region that includes a drift region. At least a portion of the drift region is provided in a membrane which has opposed top and bottom surfaces. In one embodiment, the top surface of the membrane has electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region. In another embodiment, at least one electrical terminal is connected directly or indirectly to the top surface and at least one electrical terminal is connected directly or indirectly to the bottom surface to allow a voltage to be applied vertically across the drift region. In each of these embodiments, the bottom surface of the membrane does not have a semiconductor substrate positioned adjacent thereto.

Abstract translation: 功率半导体器件具有包括漂移区域的有源区域。 漂移区域的至少一部分设置在具有相对的顶表面和底表面的膜中。 在一个实施例中，膜的顶表面具有直接或间接连接到其上的电端子，以允许跨越漂移区横向施加电压。 在另一个实施例中，至少一个电端子直接或间接地连接到顶表面，并且至少一个电端子直接或间接地连接到底表面，以允许垂直地跨越漂移区域施加电压。 在这些实施例的每一个中，膜的底表面不具有与其相邻定位的半导体衬底。

公开(公告)号：US06259134B1

公开(公告)日：2001-07-10

申请号：US09112978

申请日：1998-07-09

Applicant: Gehan A. J Amaratunga ,  Florin Udrea

Inventor： Gehan A. J Amaratunga ,  Florin Udrea

IPC: H01L2976

CPC classification number: H01L29/749 ,  H01L27/0716 ,  H01L29/42308 ,  H01L29/7455

Abstract: A MOS-controllable power semiconductor trench device has a gate in the form of a trench which extends through a region of p type silicon into an n type region of low conductivity. A discontinous buried p layer below the bottom of the trench forms part of a thyristor which in operation is triggered into conduction by conduction of a PIN diode which is produced when an accumulation layer is formed in the n type region adjacent to the trench under the action of an on-state gate signal. The device has a high on-state conductivity and is protected against high voltage breakdown in its off-state by the presence of the buried layer. An off-state gate signal causes removal of the accumulation layer and conduction of the PIN diode and the thyristor ceases in safe, reliable and rapid manner.

Abstract translation: MOS可控功率半导体沟槽器件具有沟槽形式的栅极，其延伸穿过p型硅的区域到n型低导电区域。 在沟槽底部下方的不连续埋层p层形成晶闸管的一部分，晶闸管在工作中通过PIN二极管的导通而被触发导通，该PIN二极管是当在作用下邻近沟槽的n型区域中形成蓄积层时产生的 的状态门信号。 器件具有高的导通状态，并且通过存在掩埋层来保护其处于其断开状态的高压击穿。 截止状态的栅极信号使安全，可靠和快速地停止积聚层，PIN二极管和晶闸管的导通停止。

公开(公告)号：US07605446B2

公开(公告)日：2009-10-20

申请号：US11486377

申请日：2006-07-14

Applicant: Florin Udrea ,  Nishad Udugampola ,  Gehan A. J. Amaratunga

Inventor： Florin Udrea ,  Nishad Udugampola ,  Gehan A. J. Amaratunga

IPC: H01L27/082 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L23/58

CPC classification number: H01L29/7393 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/4232 ,  H01L29/7394 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A bipolar high voltage/power semiconductor device has a drift region having adjacent its ends regions of different conductivity types respectively. High and low voltage terminals are provided. A first insulated gate terminal and a second insulated gate terminal are also provided. One or more drive circuits provide appropriate voltages to the first and second insulated gate terminals so as to allow current conduction in a first direction or in a second direction that is opposite the first direction.

Abstract translation: 双极高压/功率半导体器件具有分别具有与其不同导电类型的端部区域相邻的漂移区域。 提供高低压端子。 还提供了第一绝缘栅极端子和第二绝缘栅极端子。 一个或多个驱动电路为第一和第二绝缘栅极端子提供适当的电压，以允许在与第一方向相反的第一方向或第二方向上的电流传导。

公开(公告)号：US06900518B2

公开(公告)日：2005-05-31

申请号：US10694735

申请日：2003-10-29

Applicant: Florin Udrea ,  Gehan A. J. Amaratunga

Inventor： Florin Udrea ,  Gehan A. J. Amaratunga

IPC: H01L21/329 ,  H01L21/331 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/764 ,  H01L21/8234 ,  H01L27/08 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/12 ,  H01L29/20 ,  H01L29/24 ,  H01L29/32 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78 ,  H01L29/786 ,  H01L29/861 ,  H01L29/00 ,  H01L23/58

CPC classification number: H01L29/7816 ,  H01L21/76289 ,  H01L21/764 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/083 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/42368 ,  H01L29/66325 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7393 ,  H01L29/7394 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7801 ,  H01L29/7802 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/7824 ,  H01L29/7831 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A power semiconductor device has an active region that includes a drift region. At least a portion of the drift region is provided in a membrane which has opposed top and bottom surfaces. In one embodiment, the top surface of the membrane has electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region. In another embodiment, at least one electrical terminal is connected directly or indirectly to the top surface and at least one electrical terminal is connected directly or indirectly to the bottom surface to allow a voltage to be applied vertically across the drift region. In each of these embodiments, the bottom surface of the membrane does not have a semiconductor substrate positioned adjacent thereto.

Abstract translation: 功率半导体器件具有包括漂移区域的有源区域。 漂移区域的至少一部分设置在具有相对的顶表面和底表面的膜中。 在一个实施例中，膜的顶表面具有直接或间接连接到其上的电端子，以允许跨越漂移区横向施加电压。 在另一个实施例中，至少一个电端子直接或间接地连接到顶表面，并且至少一个电端子直接或间接地连接到底表面，以允许垂直地跨越漂移区域施加电压。 在这些实施例的每一个中，膜的底表面不具有与其相邻定位的半导体衬底。

公开(公告)号：US06703684B2

公开(公告)日：2004-03-09

申请号：US09957547

申请日：2001-09-21

Applicant: Florin Udrea ,  Gehan A. J. Amaratunga

Inventor： Florin Udrea ,  Gehan A. J. Amaratunga

IPC: H01L2900

CPC classification number: H01L29/7816 ,  H01L21/76289 ,  H01L21/764 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/083 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/42368 ,  H01L29/66325 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7393 ,  H01L29/7394 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7801 ,  H01L29/7802 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/7824 ,  H01L29/7831 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A power semiconductor device (10) has an active region that includes a drift region (20). At least a portion of the drift region (20) is provided in a membrane (16) which has opposed top and bottom surfaces (15,17). In one embodiment, the top surface (15) of the membrane (16) has electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region (20). In another embodiment, at least one electrical terminal is connected directly or indirectly to the top surface (15) and at least one electrical terminal is connected directly or indirectly to the bottom surface (17) to allow a voltage to be applied vertically across the drift region (20). In each of these embodiments, the bottom surface (17) of the membrane (16) does not have a semiconductor substrate positioned adjacent thereto.

Abstract translation: 功率半导体器件（10）具有包括漂移区（20）的有源区。 漂移区域（20）的至少一部分设置在具有相对的顶表面和底表面（15,17）的膜（16）中。 在一个实施例中，膜（16）的顶表面（15）具有直接或间接连接到其上的电端子，以允许跨越漂移区域（20）横向施加电压。 在另一个实施例中，至少一个电端子直接或间接地连接到顶表面（15），并且至少一个电端子直接或间接地连接到底表面（17），以允许垂直地施加电压跨越漂移 区域（20）。 在这些实施例的每一个中，膜（16）的底表面（17）不具有与其相邻定位的半导体衬底。

公开(公告)号：US06566240B2

公开(公告)日：2003-05-20

申请号：US09957609

申请日：2001-09-21

Applicant: Florin Udrea ,  Gehan A. J. Amaratunga

Inventor： Florin Udrea ,  Gehan A. J. Amaratunga

IPC: H01L2144

CPC classification number: H01L23/3735 ,  H01L21/84 ,  H01L2924/0002 ,  H01L2924/10158 ,  H01L2924/00

Abstract: A semiconductor device having an active region is formed in a layer provided on a semiconductor substrate. At least a portion of the semiconductor substrate below at least a portion of the active region is removed such that the portion of the active region is provided in a membrane defined by that portion of the layer below which the semiconductor substrate has been removed. A heat conducting and electrically insulating layer is applied to the bottom surface of the membrane. The heat conducting and electrically insulating layer has a thermal conductivity that is higher than the thermal conductivity of the membrane so that the heat conducting and electrically insulating layer allows heat to pass from the active region into the heat conducting and electrically insulating layer during normal operation of the device.

公开(公告)号：US07794784B2

公开(公告)日：2010-09-14

申请号：US10517257

申请日：2004-11-04

Applicant: Sajad Haq ,  Ioannis Alexandrou ,  Gehan A J Amaratunga ,  Khai H Ang

Inventor： Sajad Haq ,  Ioannis Alexandrou ,  Gehan A J Amaratunga ,  Khai H Ang

IPC: B05D7/00

CPC classification number: C04B35/62277 ,  B82Y30/00 ,  C01B32/914 ,  C04B35/62227 ,  C04B2235/405 ,  C04B2235/5264 ,  C04B2235/5284

Abstract: A method of forming a nanowire comprising: providing nanoparticles of a metallic material; providing a vapor of fluorocarbon molecules by heating a solid polymer; depositing at least some of the carbon of said molecules onto an exterior of one of said particles to form a deposit of carbon which surrounds at least part of the exterior of said one particle and assembling further of said particles with said one particle to form an elongate configuration of material in the form of a nanowire. Similar methods of production of nanotubes are also disclosed.

Abstract translation: 一种形成纳米线的方法，包括：提供金属材料的纳米颗粒; 通过加热固体聚合物提供氟碳分子的蒸气; 将所述分子的至少一些碳沉积到所述颗粒之一的外部上以形成碳沉积物，所述沉积物围绕所述一个颗粒的外部的至少一部分并且与所述一个颗粒进一步组装所述颗粒以形成细长的 配置纳米线形式的材料。 还公开了类似的纳米管生产方法。

公开(公告)号：US07531993B2

公开(公告)日：2009-05-12

申请号：US11847234

申请日：2007-08-29

Applicant: Florin Udrea ,  Nishad Udugampola ,  Gehan A. J. Amaratunga

Inventor： Florin Udrea ,  Nishad Udugampola ,  Gehan A. J. Amaratunga

IPC: G05F3/16 ,  H03K3/35

CPC classification number: H03K17/567 ,  H01L29/0638 ,  H01L29/7393 ,  H03K17/08142 ,  H03K17/6871 ,  H03K2017/6878

Abstract: A half bridge circuit has a first switch having at least one control gate and a second switch having at least two control gates. A first driver has an output connected to a control gate of the first switch. A second driver has an output connected to a first control gate of the second switch. The output of the first driver is connected to a second control gate of the second switch by a circuit arrangement such that when the first driver is operated to apply a high, positive voltage to the control gate of the first switch, a positive voltage is applied to the second control gate of the second switch, and such that when the first driver is operated to apply a low, zero or small voltage to the control gate of the first switch, a negative voltage is applied to said second control gate of the second switch.

Abstract translation: 半桥电路具有具有至少一个控制栅极的第一开关和具有至少两个控制栅极的第二开关。 第一驱动器具有连接到第一开关的控制栅极的输出端。 第二驱动器具有连接到第二开关的第一控制栅极的输出。 第一驱动器的输出通过电路装置连接到第二开关的第二控制栅极，使得当第一驱动器被操作以向第一开关的控制栅极施加高正正电压时，施加正电压 并且使得当第一驱动器被操作以向第一开关的控制栅极施加低，零或小电压时，负电压被施加到第二开关的第二控制栅极的第二控制栅极 开关。

公开(公告)号：US07235439B2

公开(公告)日：2007-06-26

申请号：US11174606

申请日：2005-07-06

Applicant: Florin Udrea ,  Gehan A J Amaratunga

Inventor： Florin Udrea ,  Gehan A J Amaratunga

IPC: H01L21/8238

CPC classification number: H01L29/7816 ,  H01L21/76289 ,  H01L21/764 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/083 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/42368 ,  H01L29/66325 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7393 ,  H01L29/7394 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7801 ,  H01L29/7802 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/7824 ,  H01L29/7831 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A power semiconductor device has an active region that includes a drift region. At least a portion of the drift region is provided in a membrane which has opposed top and bottom surfaces. In one embodiment, the top surface of the membrane has electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region. In another embodiment, at least one electrical terminal is connected directly or indirectly to the top surface and at least one electrical terminal is connected directly or indirectly to the bottom surface to allow a voltage to be applied vertically across the drift region. In each of these embodiments, the bottom surface of the membrane does not have a semiconductor substrate positioned adjacent thereto.

Abstract translation: 功率半导体器件具有包括漂移区域的有源区域。 漂移区域的至少一部分设置在具有相对的顶表面和底表面的膜中。 在一个实施例中，膜的顶表面具有直接或间接连接到其上的电端子，以允许跨越漂移区横向施加电压。 在另一个实施例中，至少一个电端子直接或间接地连接到顶表面，并且至少一个电端子直接或间接地连接到底表面，以允许垂直地跨越漂移区域施加电压。 在这些实施例的每一个中，膜的底表面不具有与其相邻定位的半导体衬底。

公开(公告)号：US07230314B2

公开(公告)日：2007-06-12

申请号：US10400541

申请日：2003-03-28

Applicant: Florin Udrea ,  Gehan A. J. Amaratunga

Inventor： Florin Udrea ,  Gehan A. J. Amaratunga

IPC: H01L21/00

CPC classification number: H01L23/3735 ,  H01L21/84 ,  H01L2924/0002 ,  H01L2924/10158 ,  H01L2924/00

Abstract: A semiconductor device having an active region is formed in a layer provided on a semiconductor substrate. At least a portion of the semiconductor substrate below at least a portion of the active region is removed such that the portion of the active region is provided in a membrane defined by that portion of the layer below which the semiconductor substrate has been removed. A heat conducting and electrically insulating layer is applied to the bottom surface of the membrane. The heat conducting and electrically insulating layer has a thermal conductivity that is higher than the thermal conductivity of the membrane so that the heat conducting and electrically insulating layer allows heat to pass from the active region into the heat conducting and electrically insulating layer during normal operation of the device.

Abstract translation: 具有有源区的半导体器件形成在设置在半导体衬底上的层中。 移除至少部分有源区的半导体衬底的至少一部分，使得有源区的一部分设置在由半导体衬底已被去除的层的该部分限定的膜中。 将导热和电绝缘层施加到膜的底表面。 导热和电绝缘层的导热率高于膜的热导率，使得导热和电绝缘层在正常操作期间允许热量从有源区域传导到导热和电绝缘层中 装置。