利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

254 条记录 (耗时 0.032 秒)

    Relaxed silicon germanium substrate with low defect density
    22.
    发明授权
    Relaxed silicon germanium substrate with low defect density 有权
    具有低缺陷密度的松弛硅锗衬底

    公开(公告)号：US06878610B1

    公开(公告)日：2005-04-12

    申请号：US10228545

    申请日：2002-08-27

    申请人： Chun Chich Lin ,  Yee-Chia Yeo ,  Chien-Chao Huang ,  Chao-Hsiung Wang ,  Tien-Chih Chang ,  Chenming Hu ,  Fu-Liang Yang ,  Shih-Chang Chen ,  Mong-Song Liang ,  Liang-Gi Yao

    发明人： Chun Chich Lin ,  Yee-Chia Yeo ,  Chien-Chao Huang ,  Chao-Hsiung Wang ,  Tien-Chih Chang ,  Chenming Hu ,  Fu-Liang Yang ,  Shih-Chang Chen ,  Mong-Song Liang ,  Liang-Gi Yao

    IPC分类号： C30B1/00 ,  H01L21/00 ,  H01L21/20 ,  H01L21/205 ,  H01L21/324 ,  H01L21/36 ,  H01L21/84 ,  H01L29/10

    CPC分类号： H01L29/1054 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/324

    摘要： A method of forming a strained silicon layer on a relaxed, low defect density semiconductor alloy layer such as SiGe, has been developed. In a first embodiment of this invention the relaxed, low density SiGe layer is epitaxially grown on an silicon layer which in turn is located on an underlying SiGe layer. During the epitaxial growth of the overlying SiGe layer defects are formed in the underlying silicon layer resulting in the desired, relaxation, and decreased defect density for the SiGe layer. A second embodiment features an anneal procedure performed during growth of the relaxed SiGe layer, resulting in additional relaxation and decreased defect density, while a third embodiment features an anneal procedure performed to the underlying silicon layer prior to epitaxial growth of the relaxed SiGe layer, again allowing optimized relaxation and defect density to be realized for the SiGe layer. The ability to obtain a strained silicon layer on a relaxed, low defect density SiGe layer, allows devices with enhanced carrier mobility to be formed in the surface of the strained silicon layer, with decreased risk of leakage due the presence of the underlying, relaxed, low defect density SiGe layer.

    摘要翻译： 已经开发了在松弛的低缺陷密度半导体合金层如SiGe上形成应变硅层的方法。 在本发明的第一实施例中，松散的低密度SiGe层在硅层上外延生长，硅层又位于下面的SiGe层上。 在覆盖SiGe层的外延生长期间，在下层硅层中形成缺陷，导致SiGe层所需的，松弛的和降低的缺陷密度。 第二个实施例的特征在于在松弛的SiGe层的生长期间执行的退火程序，导致附加的松弛和降低的缺陷密度，而第三实施例的特征在于在弛豫的SiGe层的外延生长之前对下面的硅层进行退火处理 允许为SiGe层实现优化的弛豫和缺陷密度。 在松弛的低缺陷密度SiGe层上获得应变硅层的能力允许在应变硅层的表面形成具有增强的载流子迁移率的器件，由于存在下面的，放松的， 低缺陷密度SiGe层。

    Method of forming a transistor with a strained channel
    24.
    发明授权
    Method of forming a transistor with a strained channel 有权
    形成具有应变通道的晶体管的方法

    公开(公告)号：US06492216B1

    公开(公告)日：2002-12-10

    申请号：US10068926

    申请日：2002-02-07

    申请人： Yee-Chia Yeo ,  Fu-Liang Yang ,  Chenming Hu

    发明人： Yee-Chia Yeo ,  Fu-Liang Yang ,  Chenming Hu

    IPC分类号： H01L21336

    CPC分类号： H01L29/66636 ,  H01L29/1054 ,  H01L29/41783 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/7834 ,  H01L29/7842

    摘要： A method of forming a tensile or compressive strained channel region for a semiconductor device, such as a MOSFET device, allowing improved carrier transport properties and increased device performance to be realized, has been developed. The method features the epitaxial growth of a semiconductor layer such as silicon, or silicon-germanium, with the incorporation of atoms such as carbon. The silicon-germanium-carbon channel layer, under biaxial tensile or compressive strain, is then overlaid with an optional silicon capping layer, used to accommodate the overlying, thermally grown silicon dioxide gate insulator layer, of the MOSFET device.

    摘要翻译： 已经开发了形成用于诸如MOSFET器件的半导体器件的拉伸或压缩应变通道区域的方法，其允许改进的载流子传输特性和提高的器件性能得以实现。 该方法的特征在于诸如硅或硅 - 锗的半导体层的外延生长，其中引入诸如碳的原子。 然后，在双轴拉伸或压缩应变下的硅 - 锗 - 碳通道层覆盖有用于容纳MOSFET器件的上覆的热生长二氧化硅栅极绝缘体层的任选的硅封盖层。

    Semiconductor nano-wire devices and methods of fabrication
    25.
    发明授权
    Semiconductor nano-wire devices and methods of fabrication 有权
    半导体纳米线器件及其制造方法

    公开(公告)号：US07452778B2

    公开(公告)日：2008-11-18

    申请号：US11104348

    申请日：2005-04-12

    申请人： Hung-Wei Chen ,  Yee-Chia Yeo ,  Di-Hong Lee ,  Fu-Liang Yang ,  Chenming Hu

    发明人： Hung-Wei Chen ,  Yee-Chia Yeo ,  Di-Hong Lee ,  Fu-Liang Yang ,  Chenming Hu

    IPC分类号： H01L21/336

    CPC分类号： H01L29/42384 ,  B82Y10/00 ,  H01L21/324 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/7854 ,  H01L29/78645 ,  H01L29/78696

    摘要： Nano-wires, preferably of less than 20 nm diameter, can be formed with minimized risk of narrowing and breaking that results from silicon atom migration during an annealing process step. This is accomplished by masking portion of the active layer where silicon atomer would otherwise agglomerate with a material such as silicon dioxide, silicon nitride, or other dielectric that eliminates or substantially reduces the silicon atom migration. Nano-wires, nanotubes, nano-rods, and other features can be formed and can optionally be incorporated into devices, such as by use as a channel region in a transistor device.

    摘要翻译： 可以形成直径小于20nm的纳米线，其最小化是在退火工艺步骤期间硅原子迁移导致的变窄和断裂的风险。 这是通过掩蔽有源层的一部分来实现的，其中硅一方面将以诸如二氧化硅，氮化硅或其它电介质的材料聚集，其消除或基本上减少硅原子迁移。 可以形成纳米线，纳米管，纳米棒和其它特征，并且可以可选地并入器件中，例如用作晶体管器件中的沟道区。

    Contacts to semiconductor fin devices
    26.
    发明授权
    Contacts to semiconductor fin devices 有权
    与半导体鳍片器件接触

    公开(公告)号：US07262086B2

    公开(公告)日：2007-08-28

    申请号：US11478916

    申请日：2006-06-30

    申请人： Yee-Chia Yeo ,  Fu-Liang Yang ,  Chenming Hu

    发明人： Yee-Chia Yeo ,  Fu-Liang Yang ,  Chenming Hu

    IPC分类号： H01L21/339

    CPC分类号： H01L29/785 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for forming a contact to a semiconductor fin which can be carried out by first providing a semiconductor fin that has a top surface, two sidewall surfaces and at least one end surface; forming an etch stop layer overlying the fin; forming a passivation layer overlying the etch stop layer; forming a contact hole in the passivation layer exposing the etch stop layer; removing the etch stop layer in the contact hole; and filling the contact hole with an electrically conductive material.

    摘要翻译： 一种用于形成与半导体鳍片的接触的方法，其可以通过首先提供具有顶表面，两个侧壁表面和至少一个端面的半导体鳍片来实现; 形成覆盖鳍片的蚀刻停止层; 形成覆盖所述蚀刻停止层的钝化层; 在所述钝化层中形成暴露所述蚀刻停止层的接触孔; 去除接触孔中的蚀刻停止层; 并用导电材料填充接触孔。

    Doping of semiconductor fin devices
    29.
    发明授权
    Doping of semiconductor fin devices 有权
    掺杂半导体鳍片器件

    公开(公告)号：US07074656B2

    公开(公告)日：2006-07-11

    申请号：US10425156

    申请日：2003-04-29

    申请人： Yee-Chia Yeo ,  Ping-Wei Wang ,  Hao-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

    发明人： Yee-Chia Yeo ,  Ping-Wei Wang ,  Hao-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

    IPC分类号： H01L21/84

    CPC分类号： H01L29/785 ,  H01L21/26586 ,  H01L29/66803

    摘要： A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.

    摘要翻译： 半导体结构包括覆盖绝缘体层的多个半导体鳍片，覆盖所述半导体鳍片的一部分的栅极电介质和覆盖栅极电介质的栅电极。 每个半导体翅片具有顶表面，第一侧壁表面和第二侧壁表面。 掺杂离子相对于半导体鳍片的顶表面的法线以第一角度（例如，大于约7°）注入，以掺杂第一侧壁表面和顶表面。 相对于半导体鳍片的顶表面的法线注入另外的掺杂剂离子以掺杂第二侧壁表面和顶表面。

    Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement
    30.
    发明授权
    Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement 有权
    应变平衡结构具有拉伸应变硅通道和压缩应变硅 - 锗通道，用于CMOS性能提升

    公开(公告)号：US06955952B2

    公开(公告)日：2005-10-18

    申请号：US10383709

    申请日：2003-03-07

    申请人： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Mong-Song Liang ,  Chenming Hu

    发明人： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Mong-Song Liang ,  Chenming Hu

    IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L27/12 ,  H01L31/109

    CPC分类号： H01L29/1054 ,  H01L21/84 ,  H01L27/1203

    摘要： A method of fabricating a CMOS device wherein mobility enhancement of both the NMOS and PMOS elements is realized via strain induced band structure modification, has been developed. The NMOS element is formed featuring a silicon channel region under biaxial strain while the PMOS element is simultaneously formed featuring a SiGe channel region under biaxial compressive strain. A novel process sequence allowing formation of a thicker silicon layer overlying a SiGe layer, allows the NMOS channel region to exist in the silicon layer which is under biaxial tensile stain enhancing electron mobility. The same novel process sequence results in the presence of a thinner silicon layer, overlying the same SiGe layer in the PMOS region, allowing the PMOS channel region to exist in the biaxial compressively strained SiGe layer, resulting in hole mobility enhancement.

    摘要翻译： 已经开发了通过应变诱导带结构修改来实现NMOS和PMOS元件的迁移率增强的CMOS器件的制造方法。 NMOS元件形成为具有双轴应变下的硅沟道区，同时形成在双轴压缩应变下具有SiGe沟道区的PMOS元件。 允许形成覆盖SiGe层的较厚硅层的新颖工艺顺序允许NMOS沟道区存在于双轴拉伸污染增强电子迁移率的硅层中。 相同的新工艺序列导致存在较薄的硅层，覆盖PMOS区域中相同的SiGe层，允许PMOS沟道区存在于双轴压缩应变SiGe层中，导致空穴迁移率增强。