公开(公告)号：US10242946B2

公开(公告)日：2019-03-26

申请号：US15418001

申请日：2017-01-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Irene Y. L. Lin ,  Lei Yuan ,  Mahbub Rashed

IPC: G06F17/50 ,  H01L27/02 ,  H01L23/522 ,  H01L23/528 ,  H01L27/118

Abstract: A multi-layer integrated circuit structure includes (among other components) a first layer having gate conductors, a second layer having M0 conductors, a third layer having M1 conductors, and a fourth layer having M2 conductors. The M0 and M2 conductors are perpendicular to the gate conductors, and parallel to each other. The M1 conductors connect the M0 conductors to the M2 conductors. The gate conductors are positioned in the first layer in the same locations in the horizontal direction. The M1 conductors are positioned in the third layer in a different location in the horizontal direction that is different from the locations of the gate conductors, so that the M1 conductors do not overlap any of the gate conductors, solving a substantial routing challenge for the input and output contacts.

公开(公告)号：US20170263506A1

公开(公告)日：2017-09-14

申请号：US15067953

申请日：2016-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Tuhin Guha Neogi ,  Andy Chi-Hung Wei ,  Jia Zeng ,  Jongwook Kye ,  Jason Eugene Stephens ,  Irene Yuh-Ling Lin ,  Sudharshanan Raghunathan ,  Lei Yuan

IPC: H01L21/8238 ,  H01L21/768 ,  G06F17/50 ,  H01L21/027 ,  H01L27/092 ,  H01L23/535 ,  H01L21/8234 ,  H01L21/285

CPC classification number: H01L21/823871 ,  G06F17/5072 ,  H01L21/027 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/535 ,  H01L27/0886 ,  H01L27/0924

Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.

公开(公告)号：US09679809B1

公开(公告)日：2017-06-13

申请号：US15077564

申请日：2016-03-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jongwook Kye ,  Yan Wang ,  Chenchen Wang ,  Wenhui Wang ,  Lei Yuan ,  Jia Zeng ,  Guillaume Bouche

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/28 ,  H01L45/00

CPC classification number: H01L21/28141 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76816 ,  H01L45/1691

Abstract: A method of forming a pattern for interconnect lines in an integrated circuit includes providing a structure having a first lithographic stack, a mandrel layer and a pattern layer disposed over a dielectric stack. Patterning the structure to form mandrels in the mandrel layer and disposing a spacer layer over the mandrels. Etching the spacer layer to form spacers disposed on sidewalls of the mandrels. The spacers and mandrels defining beta and gamma regions. A beta region includes a beta block mask portion and a gamma region includes a gamma block mask portion of the pattern layer. The method also includes etching a beta pillar over the beta block mask portion and etching a gamma pillar over the gamma block mask portion. The method also includes etching the structure to form a pattern in the pattern layer, the pattern including the gamma and beta block mask portions.

公开(公告)号：US09582629B2

公开(公告)日：2017-02-28

申请号：US14245868

申请日：2014-04-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Li Yang ,  Jongwook Kye

IPC: H01L21/76 ,  G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5077

Abstract: At least one method disclosed herein involves creating an overall pattern layout for an integrated circuit that is to be manufactured using a self-aligned double patterning (SADP) process, forming a first metal feature having a first width on a first track of a metal layer using the SADP process, forming a second metal feature having a second width on a second track of the metal layer. The second track is adjacent to the first track. The method also includes forming an electrical connection between the first metal feature and the second metal feature to provide an effectively single metal pattern having a third width that is the sum of the first and second widths, rendering the first and second features decomposable using the SADP process; and decomposing the overall pattern layout with the first and second metal features into a mandrel mask pattern and a block mask pattern.

Abstract translation: 本文公开的至少一种方法涉及为使用自对准双图案（SADP）工艺制造的集成电路的整体图案布局，在金属层的第一轨道上形成具有第一宽度的第一金属特征 使用SADP工艺，在金属层的第二轨道上形成具有第二宽度的第二金属特征。 第二条轨道与第一条轨道相邻。 该方法还包括在第一金属特征和第二金属特征之间形成电连接，以提供具有第三宽度的有效单个金属图案，该第三宽度是第一宽度和第二宽度之和，使得第一和第二特征可以使用SADP分解 处理; 并且将具有第一和第二金属特征的整体图案布局分解成心轴掩模图案和块掩模图案。

公开(公告)号：US09519745B2

公开(公告)日：2016-12-13

申请号：US14523558

申请日：2014-10-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Irene Lin ,  Jongwook Kye ,  Mahbub Rashed

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5077 ,  Y02T10/82

Abstract: A method and apparatus for an assisted metal routing is disclosed. Embodiments may include: determining an initial block mask having a first inner vertex for forming a metal routing layer of an integrated circuit (IC); adding an assistant metal portion within the metal routing layer; and determining a modified block mask based on the assistant metal portion for forming the metal routing layer.

Abstract translation: 公开了一种用于辅助金属布线的方法和装置。 实施例可以包括：确定具有用于形成集成电路（IC）的金属布线层的第一内部顶点的初始块掩码; 在所述金属布线层内添加辅助金属部分; 以及基于用于形成金属布线层的辅助金属部分确定修改的块掩模。

公开(公告)号：US09400863B2

公开(公告)日：2016-07-26

申请号：US14687477

申请日：2015-04-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Soo Han Choi ,  Li Yang ,  Jongwook Kye

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: Methodologies and an apparatus enabling a generation of color undeterminable polygons in IC designs are disclosed. Embodiments include: determining a plurality of first routes extending horizontally in an IC design, each of the plurality of first routes being placed on one of a plurality of equally spaced vertical positions of the IC design; determining whether a second route overlaps one of the vertical positions of the plurality of equally spaced vertical positions; and selecting a design rule for the second route based on the determination of whether the second route overlaps.

公开(公告)号：US09292647B2

公开(公告)日：2016-03-22

申请号：US14163511

申请日：2014-01-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Mahbub Rashed ,  Jongwook Kye

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  Y02T10/82

Abstract: A methodology for a modified cell architecture and the resulting devices are disclosed. Embodiments may include determining a first vertical track spacing for a plurality of first routes for an integrated circuit (IC) design, each of the plurality of first routes having a first width, determining a second vertical track spacing for a second route for the IC design, the second route having a second width, and designating a cell vertical dimension for the IC design based on the first and second vertical track spacings.

Abstract translation: 公开了修改的小区体系结构的方法以及所得到的设备。 实施例可以包括确定用于集成电路（IC）设计的多个第一路由的第一垂直轨道间隔，所述多个第一路线中的​​每一条路径具有第一宽度，确定用于IC设计的第二路线的第二垂直轨道间距 所述第二路径具有第二宽度，并且基于所述第一和第二垂直轨道间隔指定所述IC设计的单元垂直尺寸。

公开(公告)号：US08969199B1

公开(公告)日：2015-03-03

申请号：US14054251

申请日：2013-10-15

Applicant: Globalfoundries Inc.

Inventor： Lei Yuan ,  Jason Eugene Stephens ,  Li Yang ,  Soo Han Choi

IPC: H01L21/312 ,  H01L21/033 ,  H01L21/768

CPC classification number: H01L21/0334 ,  H01L21/31144 ,  H01L21/76895 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11859

Abstract: One illustrative method disclosed herein includes, among other things, patterning a hard mask layer using three patterned photoresist etch masks, wherein a first feature corresponding to a portion, but not all, of a cross-coupling gate contact structure is present in a first of the three patterned photoresist etch masks and a second feature corresponding to a portion, but not all, of the cross-coupling gate contact structure is present in a second or a third of the three patterned photoresist etch masks, patterning a layer of insulating material using the patterned hard mask layer as an etch mask, and forming a cross-coupling gate contact structure in a trench in the layer of insulating material.

Abstract translation: 本文公开的一种说明性方法包括使用三种图案化的光致抗蚀剂蚀刻掩模图案化硬掩模层，其中对应于交叉耦合栅极接触结构的一部分但不是全部的第一特征存在于第一 三个图案化的光致抗蚀剂蚀刻掩模和对应于交叉耦合栅极接触结构的一部分但不是全部的第二特征存在于三个图案化的光致抗蚀剂蚀刻掩模的第二或第三个中，使用 图案化的硬掩模层作为蚀刻掩模，并且在绝缘材料层中的沟槽中形成交叉耦合栅极接触结构。

公开(公告)号：US20140327146A1

公开(公告)日：2014-11-06

申请号：US13874803

申请日：2013-05-01

Applicant: Globalfoundries Inc

Inventor： Yunfei Deng ,  Lei Yuan ,  Hidekazu Yoshida ,  Juhan Kim ,  Mahbub Rashed ,  Jongwook Kye

IPC: G06F17/50 ,  H01L23/48

CPC classification number: G06F17/5077 ,  G06F17/5072 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11831 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A design methodology for routing for an integrated circuit is disclosed. The method includes placement of cells having double diffusion breaks, which create an extended intercell region. Metal layer prohibit zones are defined to prohibit any M1 structures in the prohibit zones. Metal layer allow zones are placed adjacent to outer metal lines, and jogs are formed in the metal layer allow zones. Vias and viabars may then be applied on the jogs.

Abstract translation: 公开了用于集成电路布线的设计方法。 该方法包括放置具有双扩散断裂的电池，这产生扩展的电池间​​区域。 金属层禁止区被定义为禁止禁区内的任何M1结构。 金属层允许区域邻近外部金属线放置，并且在金属层中形成点动允许区域。 然后将通风口和viabars应用于慢跑。

公开(公告)号：US08843869B1

公开(公告)日：2014-09-23

申请号：US13838378

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Jongwook Kye ,  Harry Levinson

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A method and apparatus for insertion of a via improving a manufacturability of a resulting device while ensuring compliance with DRC rules are disclosed. Embodiments include: determining a layer of a substrate of an IC design having a first via and a plurality of routes, the plurality of routes extending horizontally on the substrate and placed on one of a plurality of equally spaced vertical positions; comparing a region of the layer extending vertically between a first set of the plurality of routes and extending horizontally between a second set of the plurality of the routes with one or more threshold values, the region being adjacent to the first via and being separated from the plurality of routes; and inserting a second via based on the comparison.

Abstract translation: 公开了一种用于插入通孔的方法和装置，其改善了所得到的装置的可制造性，同时确保符合DRC规则。 实施例包括：确定具有第一通孔和多个路线的IC设计的基板的层，所述多个路线在基板上水平延伸并且放置在多个等间隔的垂直位置中的一个上; 比较在多个路线的第一组之间垂直延伸并且在第二组多个路线之间水平延伸的层的区域与一个或多个阈值，所述区域与第一通孔相邻并且与第一通孔分离 多条路线; 以及基于所述比较来插入第二通孔。