公开(公告)号：US09608110B2

公开(公告)日：2017-03-28

申请号：US14812245

申请日：2015-07-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Carsten Grass

IPC: H01L21/00 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L29/51 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/11592

CPC classification number: H01L29/78391 ,  H01L21/28185 ,  H01L21/28291 ,  H01L21/823462 ,  H01L21/823857 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/1159 ,  H01L27/11592 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66545

Abstract: The present disclosure provides methods of forming a semiconductor circuit element and a semiconductor circuit element, wherein the semiconductor circuit element includes a first semiconductor device with a first gate structure disposed over a first active region of a semiconductor substrate and a second semiconductor device with a second gate structure disposed over a second active region of the semiconductor substrate, the first gate structure comprising a ferroelectric material buried into the first active region before a gate electrode material is formed on the ferroelectric material and the second gate structure comprising a high-k material different from the ferroelectric material.

公开(公告)号：US09564521B2

公开(公告)日：2017-02-07

申请号：US15076850

申请日：2016-03-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Till Schloesser ,  Peter Baars

IPC: H01L21/336 ,  H01L21/44 ,  H01L29/66 ,  H01L21/28 ,  H01L29/51 ,  H01L27/115 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/6684 ,  H01L21/28291 ,  H01L21/823462 ,  H01L27/11509 ,  H01L29/516 ,  H01L29/78391

Abstract: A semiconductor device comprises a first and second circuit element. The first circuit element comprises a first electrode structure including a first high-k dielectric layer, the first high-k dielectric layer having a first thickness and comprising hafnium. The second circuit element comprises a second electrode structure that includes a second high-k dielectric layer having a ferroelectric behavior, wherein the second high-k dielectric layer has a second thickness and comprises hafnium, and wherein the second thickness is greater than the first thickness.

Abstract translation: 半导体器件包括第一和第二电路元件。 第一电路元件包括包括第一高k电介质层的第一电极结构，第一高k电介质层具有第一厚度并且包含铪。 第二电路元件包括第二电极结构，其包括具有铁电性能的第二高k电介质层，其中第二高k电介质层具有第二厚度并且包括铪，并且其中第二厚度大于第一厚度 。

公开(公告)号：US20160247891A1

公开(公告)日：2016-08-25

申请号：US14628947

申请日：2015-02-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Peter Baars ,  Thorsten Kammler

IPC: H01L29/49 ,  H01L23/535 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L23/535 ,  H01L21/823842 ,  H01L23/485 ,  H01L27/092 ,  H01L29/4966

Abstract: A semiconductor structure includes a substrate, at least one electrically conductive pillar provided over the substrate and an electrically conductive structure provided over the substrate. The electrically conductive pillar includes an inner portion and an outer layer that is provided below the inner portion and lateral to the inner portion. The electrically conductive structure also includes an inner portion and an outer layer that is provided below the inner portion and lateral to the inner portion. The electrically conductive structure annularly encloses each of the at least one electrically conductive pillar. The outer layer of each of the at least one electrically conductive pillar contacts the outer layer of the electrically conductive structure. The outer layer of the at least one electrically conductive pillar and the outer layer of the electrically conductive structure are formed of different metallic materials.

Abstract translation: 半导体结构包括衬底，设置在衬底上的至少一个导电柱和设置在衬底上的导电结构。 导电柱包括内部和外层，其设置在内部的下方并且在内部的侧面。 导电结构还包括内部部分和外层，其设置在内部部分的下方并且在内部部分的外侧。 导电结构环形地包围至少一个导电柱中的每一个。 所述至少一个导电柱中的每一个的外层与导电结构的外层接触。 至少一个导电柱的外层和导电结构的外层由不同的金属材料形成。

公开(公告)号：US09391156B2

公开(公告)日：2016-07-12

申请号：US14471546

申请日：2014-08-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Peter Baars ,  Jan Hoentschel

IPC: H01L49/02 ,  H01L21/28 ,  H01L29/49 ,  H01L27/06 ,  H01L23/522

CPC classification number: H01L29/4983 ,  H01L21/28088 ,  H01L21/28105 ,  H01L21/28132 ,  H01L23/5223 ,  H01L27/0629 ,  H01L28/86 ,  H01L29/4966 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device is provided, including forming a gate electrode of a dummy transistor device on a semiconductor substrate, forming a high-k material layer over and adjacent to the gate electrode and forming a metal layer on the high-k material layer over and adjacent to the gate electrode to form a capacitor.

Abstract translation: 提供一种制造半导体器件的方法，包括在半导体衬底上形成虚设晶体管器件的栅电极，在栅极上形成高k材料层并在栅极上形成高k材料层，并在高k材料上形成金属层 层叠并与栅电极相邻以形成电容器。

公开(公告)号：US20160064471A1

公开(公告)日：2016-03-03

申请号：US14471546

申请日：2014-08-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Peter Baars ,  Jan Hoentschel

IPC: H01L49/02 ,  H01L21/28 ,  H01L29/49 ,  H01L27/06

CPC classification number: H01L29/4983 ,  H01L21/28088 ,  H01L21/28105 ,  H01L21/28132 ,  H01L23/5223 ,  H01L27/0629 ,  H01L28/86 ,  H01L29/4966 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device is provided, including forming a gate electrode of a dummy transistor device on a semiconductor substrate, forming a high-k material layer over and adjacent to the gate electrode and forming a metal layer on the high-k material layer over and adjacent to the gate electrode to form a capacitor.

Abstract translation: 提供一种制造半导体器件的方法，包括在半导体衬底上形成虚设晶体管器件的栅电极，在栅极上形成高k材料层并在栅极上形成高k材料层，并在高k材料上形成金属层 层叠并与栅电极相邻以形成电容器。

公开(公告)号：US20160049302A1

公开(公告)日：2016-02-18

申请号：US14458718

申请日：2014-08-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Carsten Grass ,  Peter Baars

IPC: H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/51

CPC classification number: H01L21/28194 ,  H01L21/28185 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66545

Abstract: The present disclosure provides a method of forming a semiconductor circuit element and a semiconductor circuit element, wherein the semiconductor circuit element is formed on the basis of a replacement gate process replacing a dummy gate structure of a semiconductor device of the semiconductor circuit element by a gate oxide structure and a gate electrode material, wherein the gate oxide structure comprises a high-k material that is in the ferroelectric phase. In some illustrative embodiments herein, a semiconductor device is provided, the semiconductor device having a gate structure disposed over an active region of a semiconductor substrate. Herein, the gate structure comprises a spacer structure and a dummy gate structure which is replaced by a gate oxide structure and a gate electrode material, wherein the gate oxide structure comprises a ferroelectric high-k material.

Abstract translation: 本公开提供了一种形成半导体电路元件和半导体电路元件的方法，其中，基于替换栅极工艺形成半导体电路元件，替代栅极工艺通过栅极替代半导体电路元件的半导体器件的伪栅极结构 氧化物结构和栅电极材料，其中栅极氧化物结构包括处于铁电相中的高k材料。 在本文的一些说明性实施例中，提供半导体器件，该半导体器件具有设置在半导体衬底的有源区上方的栅极结构。 这里，栅极结构包括由栅极氧化物结构和栅电极材料代替的间隔结构和虚拟栅极结构，其中栅极氧化物结构包括铁电高k材料。

公开(公告)号：US09136175B2

公开(公告)日：2015-09-15

申请号：US14027837

申请日：2013-09-16

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Andy Wei ,  Peter Baars ,  Erik P. Geiss

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L21/768 ,  H01L21/762

CPC classification number: H01L21/823418 ,  H01L21/76224 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: Methods are provided for fabricating integrated circuits. One method includes etching a plurality of trenches into a silicon substrate and filling the trenches with an insulating material to delineate a plurality of spaced apart silicon fins. A layer of undoped silicon is epitaxially grown to form an upper, undoped region of the fins. Dummy gate structures are formed overlying and transverse to the plurality of fins and a back fill material fills between the dummy gate structures. The dummy gate structures are removed to expose a portion of the fins and a high-k dielectric material and a work function determining gate electrode material are deposited overlying the portion of the fins. The back fill material is removed to expose a second portion and metal silicide contacts are formed on the second portion. Conductive contacts are then formed to the work function determining material and to the metal silicide.

Abstract translation: 提供了用于制造集成电路的方法。 一种方法包括将多个沟槽蚀刻成硅衬底并用绝缘材料填充沟槽以描绘多个间隔开的硅片。 外延生长一层未掺杂的硅以形成翅片的上部未掺杂区域。 虚拟门结构形成为覆盖并横向于多个翅片，并且后填充材料填充在虚拟栅极结构之间。 去除虚拟栅极结构以暴露一部分散热片，并且将高k电介质材料和确定栅极电极材料的功函数沉积在鳍片的该部分上。 去除后填充材料以暴露第二部分，并且在第二部分上形成金属硅化物接触。 然后，将导电触点形成到功函数确定材料和金属硅化物。

公开(公告)号：US20130270619A1

公开(公告)日：2013-10-17

申请号：US13793645

申请日：2013-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Till Schloesser ,  Peter Baars

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/6684 ,  H01L21/28291 ,  H01L21/823462 ,  H01L27/11509 ,  H01L29/516 ,  H01L29/78391

Abstract: Ferroelectric circuit elements, such as field effect transistors or capacitors, may be formed on the basis of hafnium oxide, which may also be used during the fabrication of sophisticated high-k metal gate electrode structures of fast transistors. To this end, the hafnium-based oxide having appropriate thickness and material composition may be patterned at any appropriate manufacturing stage, without unduly affecting the overall process flow for fabricating a sophisticated high-k metal gate electrode structure.

Abstract translation: 可以在氧化铪的基础上形成诸如场效应晶体管或电容器的铁电电路元件，其也可以在制造快速晶体管的复杂高k金属栅电极结构期间使用。 为此，可以在任何合适的制造阶段对具有适当厚度和材料组成的铪基氧化物进行图案化，而不会不利地影响用于制造复杂的高k金属栅电极结构的整个工艺流程。

公开(公告)号：US10727236B2

公开(公告)日：2020-07-28

申请号：US16229600

申请日：2018-12-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nan Wu ,  Peter Baars

IPC: H01L27/11 ,  H01L27/088 ,  G11C11/412

Abstract: Structures that include stacked field-effect transistors and methods for forming a structure that includes stacked field-effect transistors. A structure includes a first fin, a second fin arranged over the first fin, a first dielectric layer between the first fin and the second fin, and a first inverter. The first inverter includes a first field-effect transistor with a channel region in the first fin and a second field-effect transistor with a channel region in the second fin. The first field-effect transistor and the second field-effect transistor share a first gate structure having an overlapping arrangement with the channel region in the first fin and the channel region in the second fin. The first fin has a longitudinal axis, and the second fin has a longitudinal axis that is aligned at an angle relative to the longitudinal axis of the first fin.

公开(公告)号：US20190252522A1

公开(公告)日：2019-08-15

申请号：US15897570

申请日：2018-02-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Juergen Thees ,  Peter Baars ,  Elliot John Smith

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/786 ,  H01L29/423 ,  H01L27/12 ,  H01L21/306 ,  H01L21/285

Abstract: A method of manufacturing a semiconductor device is provided including providing an SOI substrate comprising a semiconductor bulk substrate, a buried insulation layer and a semiconductor layer, forming a shallow trench isolation in the SOI substrate, forming a FET in and over the SOI substrate, and forming a contact to a source or drain region of the FET that is positioned adjacent to the source or drain region, wherein forming the shallow trench isolation includes forming a trench in the SOI substrate, filling a lower portion of the trench with a first dielectric layer, forming a buffer layer over the first dielectric material layer, the buffer layer having a material different from a material of the first dielectric layer, and forming a second dielectric layer over the buffer layer and of a material different from the material of the buffer layer.