公开(公告)号：US20160380067A1

公开(公告)日：2016-12-29

申请号：US14747385

申请日：2015-06-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Renata Camillo-Castillo ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/423 ,  H01L21/306 ,  H01L29/08 ,  H01L29/732 ,  H01L29/66

CPC classification number: H01L29/0821 ,  H01L21/30608 ,  H01L29/0653 ,  H01L29/0804 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/7371

Abstract: Device structure and fabrication methods for a bipolar junction transistor. An emitter layer is formed on a base layer and etched to form an emitter of the device structure. The emitter layer has a concentration of an element that varies as a function of the thickness of the emitter layer. The etch rate of the emitter layer varies as a function of the concentration of the element such that the emitter has a variable width over the thickness of the emitter layer.

Abstract translation: 双极结型晶体管的器件结构和制造方法。 发射极层形成在基底层上并被蚀刻以形成器件结构的发射极。 发射极层具有作为发射极层的厚度的函数而变化的元素的浓度。 发射极层的蚀刻速率作为元件的浓度的函数而变化，使得发射极在发射极层的厚度上具有可变的宽度。

公开(公告)号：US20210066474A1

公开(公告)日：2021-03-04

申请号：US16551061

申请日：2019-08-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Qizhi Liu ,  Vibhor Jain ,  John J. Pekarik

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/737 ,  H01L21/02

Abstract: Device structures and fabrication methods for a bipolar junction transistor. A trench isolation region surrounds an active region that includes a collector. A base layer includes a first section and a second section that are located over the active region. An emitter is positioned on the first section of the base layer, and an extrinsic base layer is positioned on the second section of the base layer. The extrinsic base layer has a side surface adjacent to the emitter. The side surface of the extrinsic base layer is inclined relative to a top surface of the base layer in a direction away from the emitter.

公开(公告)号：US10312356B1

公开(公告)日：2019-06-04

申请号：US16013363

申请日：2018-06-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Qizhi Liu ,  Vibhor Jain ,  James W. Adkisson ,  Sarah McTaggart ,  Mark Levy

IPC: H01L31/0328 ,  H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/423 ,  H01L21/762 ,  H01L29/66 ,  H01L21/306 ,  H01L21/02 ,  H01L29/06 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/265

Abstract: Device structures and fabrication methods for heterojunction bipolar transistors. Trench isolation regions are arranged to surround a plurality of active regions, and a collector is located in each of the active regions. A base layer includes a plurality of first sections that are respectively arranged over the active regions and a plurality of second sections that are respectively arranged over the trench isolation regions. The first sections of the base layer contain single-crystal semiconductor material, and the second sections of the base layer contain polycrystalline semiconductor material. The second sections of the base layer are spaced in a vertical direction from the trench isolation regions to define a plurality of cavities. A plurality of emitter fingers are respectively arranged on the first sections of the base layer.

公开(公告)号：US10121884B2

公开(公告)日：2018-11-06

申请号：US15806532

申请日：2017-11-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Qizhi Liu

IPC: H01L21/8249 ,  H01L21/8222 ,  H01L21/8228 ,  H01L27/082 ,  H01L29/737 ,  H01L29/66 ,  H01L21/8226 ,  H01L29/161 ,  H01L29/165 ,  H01L29/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L27/06 ,  H01L29/732 ,  H03F3/213

Abstract: Methods according to the present disclosure include: providing a substrate including: a first semiconductor region, a second semiconductor region, and a trench isolation (TI) laterally between the first and second semiconductor regions; forming an epitaxial layer on at least the first semiconductor region of the substrate, wherein the epitaxial layer includes a first semiconductor base material positioned above the first semiconductor region of the substrate; forming an insulator region on at least the first semiconductor base material, the trench isolation (TI), and the second semiconductor region; forming a first opening in the insulator over the second semiconductor region; and growing a second semiconductor base material in the first opening, wherein a height of the second semiconductor base material above the substrate is greater than a height of the first semiconductor base material above the substrate.

公开(公告)号：US20180286968A1

公开(公告)日：2018-10-04

申请号：US15473043

申请日：2017-03-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  Qizhi Liu ,  Alvin J. Joseph ,  Pernell Dongmo

IPC: H01L29/732 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L21/311 ,  H01L21/02 ,  H01L29/737 ,  H01L29/165

CPC classification number: H01L29/732 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/31111 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/165 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/7371

Abstract: Fabrication methods and device structures for bipolar junction transistors and heterojunction bipolar transistors. A first dielectric layer is formed and a second dielectric layer is formed on the first dielectric layer. An opening is etched extending vertically through the first dielectric layer and the second dielectric layer. A collector is formed inside the opening. An intrinsic base, which is also formed inside the opening, has a vertical arrangement relative to the collector.

公开(公告)号：US10014397B1

公开(公告)日：2018-07-03

申请号：US15383171

申请日：2016-12-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  Qizhi Liu ,  David L. Harame ,  Renata Camillo-Castillo

IPC: H01L29/737 ,  H01L29/06 ,  H01L29/66 ,  H01L29/165 ,  H01L29/417 ,  H01L21/265 ,  H01L29/735 ,  H01L27/12

Abstract: Device structures and fabrication methods for a bipolar junction transistor. The device structure includes an intrinsic base, an emitter having a vertical arrangement relative to the intrinsic base, and a collector having a lateral arrangement relative to the intrinsic base. The device structure may be fabricated by forming the intrinsic base and the collector in a semiconductor layer, and epitaxially growing the emitter on the intrinsic base and with a vertical arrangement relative to the intrinsic base. The collector and the intrinsic base have a lateral arrangement within the semiconductor layer.

公开(公告)号：US20170365695A1

公开(公告)日：2017-12-21

申请号：US15187860

申请日：2016-06-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Qizhi Liu

IPC: H01L29/737 ,  H01L21/8228 ,  H01L21/8226 ,  H01L29/04 ,  H03F3/213 ,  H01L21/8222 ,  H01L29/165 ,  H01L29/161 ,  H01L27/082 ,  H01L29/66

CPC classification number: H01L29/7378 ,  H01L21/8222 ,  H01L21/8226 ,  H01L21/82285 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0823 ,  H01L27/0826 ,  H01L29/04 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/66287 ,  H01L29/7322 ,  H01L29/7371 ,  H03F3/213 ,  H03F2200/294

Abstract: Methods of according to the present disclosure can include: providing a substrate including: a first semiconductor region, a second semiconductor region, and a trench isolation (TI) laterally between the first and second semiconductor regions; forming a seed layer on the TI and the second semiconductor region of the substrate, leaving the first semiconductor region of the substrate exposed; forming an epitaxial layer on the substrate and the seed layer, wherein the epitaxial layer includes: a first semiconductor base material positioned above the first semiconductor region of the substrate, and an extrinsic base region positioned above the seed layer; forming an opening within the extrinsic base material and the seed layer to expose an upper surface of the second semiconductor region; and forming a second semiconductor base material in the opening.

公开(公告)号：US09847408B1

公开(公告)日：2017-12-19

申请号：US15187860

申请日：2016-06-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Qizhi Liu

IPC: H01L21/331 ,  H01L21/8228 ,  H01L27/082 ,  H01L29/66 ,  H01L29/737 ,  H01L29/161 ,  H01L29/165 ,  H01L29/04 ,  H01L21/8222 ,  H03F3/213 ,  H01L21/8226

CPC classification number: H01L29/7378 ,  H01L21/8222 ,  H01L21/8226 ,  H01L21/82285 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0823 ,  H01L27/0826 ,  H01L29/04 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/66287 ,  H01L29/7322 ,  H01L29/7371 ,  H03F3/213 ,  H03F2200/294

Abstract: Methods of according to the present disclosure can include: providing a substrate including: a first semiconductor region, a second semiconductor region, and a trench isolation (TI) laterally between the first and second semiconductor regions; forming a seed layer on the TI and the second semiconductor region of the substrate, leaving the first semiconductor region of the substrate exposed; forming an epitaxial layer on the substrate and the seed layer, wherein the epitaxial layer includes: a first semiconductor base material positioned above the first semiconductor region of the substrate, and an extrinsic base region positioned above the seed layer; forming an opening within the extrinsic base material and the seed layer to expose an upper surface of the second semiconductor region; and forming a second semiconductor base material in the opening.

公开(公告)号：US20170288033A1

公开(公告)日：2017-10-05

申请号：US15626241

申请日：2017-06-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Renata Camillo-Castillo ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/08 ,  H01L29/732 ,  H01L21/306

CPC classification number: H01L29/0821 ,  H01L21/30608 ,  H01L29/0653 ,  H01L29/0804 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/7371

Abstract: Device structure and fabrication methods for a bipolar junction transistor. An emitter layer is formed on a base layer and etched to form an emitter of the device structure. The emitter layer has a concentration of an element that varies as a function of the thickness of the emitter layer. The etch rate of the emitter layer varies as a function of the concentration of the element such that the emitter has a variable width over the thickness of the emitter layer.

公开(公告)号：US20160211345A1

公开(公告)日：2016-07-21

申请号：US14601655

申请日：2015-01-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hanyi Ding ,  Vibhor Jain ,  Qizhi Liu

IPC: H01L29/66 ,  H01L29/73 ,  H01L29/08 ,  H01L21/306

CPC classification number: H01L29/66234 ,  H01L21/306 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/0804 ,  H01L29/0826 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/73 ,  H01L29/732 ,  H01L29/7371

Abstract: Device structures for a bipolar junction transistor and methods of fabricating a device structure for a bipolar junction transistor. A first semiconductor layer is formed on a substrate, and a second semiconductor layer is formed on the first semiconductor layer. The first semiconductor layer, the second semiconductor layer, and the substrate are etched to define first and second emitter fingers from the second semiconductor layer and trenches in the substrate that are laterally positioned between the first and second emitter fingers. The first semiconductor layer may function as a base layer in the device structure.

Abstract translation: 用于双极结晶体管的器件结构以及制造用于双极结型晶体管的器件结构的方法。 在基板上形成第一半导体层，在第一半导体层上形成第二半导体层。 蚀刻第一半导体层，第二半导体层和衬底以限定来自第二半导体层的第一和第二发射极指状物以及横向位于第一和第二发射极指之间的衬底中的沟槽。 第一半导体层可以用作器件结构中的基层。