公开(公告)号：US20160163707A1

公开(公告)日：2016-06-09

申请号：US15016612

申请日：2016-02-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Eric C.T. Harley ,  Judson R. Holt ,  Gauri V. Karve ,  Yue Ke ,  Derrick Liu ,  Timothy J. McArdle ,  Shogo Mochizuki ,  Alexander Reznicek ,  Melissa Alyson Smith

IPC: H01L27/092 ,  H01L29/08 ,  H01L29/161 ,  H01L29/10

CPC classification number: H01L27/0924 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/36 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Embodiments of the present invention provide a method for epitaxially growing a FinFET. One method may include providing a semiconductor substrate including an insulator and an underlayer; forming a channel layer on the semiconductor substrate using epitaxial growth; etching a recess into the channel layer and epitaxially regrowing a portion on the channel layer; etching the channel layer and the underlayer to form fins; forming a gate structure and a set of spacers; etching a source drain region into the channel layer; and forming a source drain material in the source drain region.

Abstract translation: 本发明的实施例提供了一种外延生长FinFET的方法。 一种方法可以包括提供包括绝缘体和底层的半导体衬底; 使用外延生长在所述半导体衬底上形成沟道层; 将凹槽蚀刻到沟道层中并外延地再生沟道层上的一部分; 蚀刻通道层和底层以形成翅片; 形成栅极结构和一组间隔物; 将源漏区蚀刻到沟道层中; 以及在源极漏极区域中形成源极漏极材料。

公开(公告)号：US10381442B2

公开(公告)日：2019-08-13

申请号：US15954300

申请日：2018-04-16

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Oleg Gluschenkov ,  Zuoguang Liu ,  Shogo Mochizuki ,  Hiroaki Niimi ,  Chun-chen Yeh

IPC: H01L29/08 ,  H01L29/161 ,  H01L29/167 ,  H01L29/417 ,  H01L21/324 ,  H01L21/02 ,  H01L21/265 ,  H01L29/45 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78 ,  H01L21/285 ,  H01L21/8238

Abstract: Techniques for forming Ga-doped source drain contacts in Ge-based transistors are provided. In one aspect, a method for forming Ga-doped source and drain contacts includes the steps of: depositing a dielectric over a transistor; depositing a dielectric over the transistor; forming contact trenches in the dielectric over, and extending down to, source and drain regions of the transistor; depositing an epitaxial material into the contact trenches; implanting gallium ions into the epitaxial material to form an amorphous gallium-doped layer; and annealing the amorphous gallium-doped layer under conditions sufficient to form a crystalline gallium-doped layer having a homogenous gallium concentration of greater than about 5×1020 at./cm3. Transistor devices are also provided utilizing the present Ga-doped source and drain contacts.

公开(公告)号：US20180240875A1

公开(公告)日：2018-08-23

申请号：US15954300

申请日：2018-04-16

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Oleg Gluschenkov ,  Zuoguang Liu ,  Shogo Mochizuki ,  Hiroaki Niimi ,  Chun-chen Yeh

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/285 ,  H01L21/324 ,  H01L21/8238 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/45

CPC classification number: H01L29/0847 ,  H01L21/02057 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/823814 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: Techniques for forming Ga-doped source drain contacts in Ge-based transistors are provided. In one aspect, a method for forming Ga-doped source and drain contacts includes the steps of: depositing a dielectric over a transistor; depositing a dielectric over the transistor; forming contact trenches in the dielectric over, and extending down to, source and drain regions of the transistor; depositing an epitaxial material into the contact trenches; implanting gallium ions into the epitaxial material to form an amorphous gallium-doped layer; and annealing the amorphous gallium-doped layer under conditions sufficient to form a crystalline gallium-doped layer having a homogenous gallium concentration of greater than about 5×1020 at./cm3. Transistor devices are also provided utilizing the present Ga-doped source and drain contacts.

公开(公告)号：US09972682B2

公开(公告)日：2018-05-15

申请号：US15004756

申请日：2016-01-22

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Oleg Gluschenkov ,  Zuoguang Liu ,  Shogo Mochizuki ,  Hiroaki Niimi ,  Chun-chen Yeh

IPC: H01L29/08 ,  H01L29/161 ,  H01L29/167 ,  H01L29/417 ,  H01L21/324 ,  H01L21/02 ,  H01L21/265 ,  H01L29/45 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78 ,  H01L21/285 ,  H01L21/8238

CPC classification number: H01L29/0847 ,  H01L21/02057 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/823814 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: Techniques for forming Ga-doped source drain contacts in Ge-based transistors are provided. In one aspect, a method for forming Ga-doped source and drain contacts includes the steps of: depositing a dielectric over a transistor; depositing a dielectric over the transistor; forming contact trenches in the dielectric over, and extending down to, source and drain regions of the transistor; depositing an epitaxial material into the contact trenches; implanting gallium ions into the epitaxial material to form an amorphous gallium-doped layer; and annealing the amorphous gallium-doped layer under conditions sufficient to form a crystalline gallium-doped layer having a homogenous gallium concentration of greater than about 5×1020 at./cm3. Transistor devices are also provided utilizing the present Ga-doped source and drain contacts.

公开(公告)号：US20170301697A1

公开(公告)日：2017-10-19

申请号：US15098722

申请日：2016-04-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Alexander Reznicek ,  Veeraraghavan S. Basker ,  Shogo Mochizuki ,  Nicolas L. Breil ,  Oleg Gluschenkov

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/324 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3115

CPC classification number: H01L27/1211 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02623 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/01 ,  H01L27/0886 ,  H01L29/161 ,  H01L29/6653 ,  H01L29/7848

Abstract: Relaxed silicon germanium fins are formed on a bulk silicon substrate through the lateral recrystallization of molten silicon germanium having high germanium content. Following formation of the silicon germanium fins, the silicon is selectively recessed.The resulting trenches are filled with electrically insulating material and then recessed down to the bottoms of the fins.

公开(公告)号：US09496341B1

公开(公告)日：2016-11-15

申请号：US14730320

申请日：2015-06-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Judson Holt ,  Shogo Mochizuki

IPC: H01L29/47 ,  H01L29/10 ,  H01L29/78 ,  H01L29/16 ,  H01L29/161 ,  H01L21/02 ,  H01L21/306 ,  H01L21/324 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L29/1054 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/18 ,  H01L21/7624 ,  H01L29/161 ,  H01L29/785

Abstract: A method includes forming a multilayered stack on a surface of a supporting layer. The multilayered stack is composed of alternating layers of compressively strained Silicon Germanium (Si1-xGex) and tensily strained Carbon-doped Silicon (Si:C). The method further includes etching the multilayered stack to form at least one Fin precursor structure and annealing the Fin precursor structure to remove Carbon from the strained Si:C layers to form Carbon-depleted layers and to diffuse Germanium from the Si1-xGex layers into the Carbon-depleted layers producing a Si1-xGex Fin. A structure that is disclosed includes a Semiconductor on Insulator (SOI) layer disposed on a layer of buried oxide and a multilayered stack on a surface of the SOI layer. The multilayered stack is composed of alternating layers of compressively strained Si1-xGex and tensily strained Si:C. The structure further includes a hardmask layer disposed on a top surface of the multilayered stack.

Abstract translation: 一种方法包括在支撑层的表面上形成多层叠层。 多层堆叠由压缩应变硅锗（Si1-xGex）和紧张应变碳掺杂硅（Si：C）的交替层组成。 该方法还包括蚀刻多层堆叠以形成至少一个Fin前体结构并退火Fin前体结构以从应变的Si：C层去除碳以形成贫碳层并将锗从Si1-xGex层扩散到 生产Si1-xGex Fin的碳耗尽层。 所公开的结构包括在SOI层的表面上设置在掩埋氧化物层和多层叠层上的半导体绝缘体（SOI）层。 多层堆叠由压缩应变Si1-xGex和紧张应变Si：C的交替层组成。 该结构还包括设置在多层堆叠的顶表面上的硬掩模层。

公开(公告)号：US20160133727A1

公开(公告)日：2016-05-12

申请号：US14537832

申请日：2014-11-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Pouya Hashemi ,  Shogo Mochizuki ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/08 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor structure, such as a FinFET, etc., includes a bi-portioned junction. The bi-portioned junction includes a doped outer portion and a doped inner portion. The dopant concentration of the outer portion is less than the dopant concentration of the inner portion. An electrical connection is formed by diffusion of the dopants within outer portion into a channel region and diffusion of the dopants within the outer portion into the inner region. A low contact resistance is achieved by a contact electrically contacting the relatively higher doped inner portion while device shorting is limited by the relatively lower doped outer portion.

Abstract translation: 诸如FinFET等的半导体结构包括双分支结。 双分支结包括掺杂的外部部分和掺杂的内部部分。 外部部分的掺杂剂浓度小于内部部分的掺杂剂浓度。 通过将外部部分内的掺杂剂扩散到沟道区域中并且将外部部分内的掺杂剂扩散到内部区域中来形成电连接。 低接触电阻通过电接触相对较高的掺杂内部部分的接触来实现，同时器件短路由相对较低的掺杂外部部分限制。