公开(公告)号：US20200279768A1

公开(公告)日：2020-09-03

申请号：US16290178

申请日：2019-03-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vimal K. Kamineni ,  Ruilong Xie ,  Kangguo Cheng ,  Adra V. Carr

IPC: H01L21/768 ,  H01L23/532

Abstract: Structures that include a field effect-transistor and methods of forming a structure that includes a field-effect transistor. A first field-effect transistor includes a first source/drain region, and a second field-effect transistor includes a second source/drain region. A first contact is arranged over the first source/drain region, and a second contact is arranged over the second source/drain region. A portion of a dielectric layer, which is composed of a low-k dielectric material, is laterally arranged between the first contact and the second contact.

公开(公告)号：US10741668B2

公开(公告)日：2020-08-11

申请号：US15654234

申请日：2017-07-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bala Haran ,  Ruilong Xie ,  Balaji Kannan ,  Katsunori Onishi ,  Vimal K. Kamineni

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/161 ,  H01L21/285 ,  H01L29/78 ,  H01L27/092

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to replacement metal gate structures and methods of manufacture. The structure includes at least one short channel device including a dielectric material, a workfunction metal, and a capping material, and a long channel device comprising the dielectric material, the workfunction metal and fluorine free gate conductor material.

公开(公告)号：US10546785B2

公开(公告)日：2020-01-28

申请号：US15454445

申请日：2017-03-09

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES INC. ,  Lam Research Corporation

Inventor： Georges Jacobi ,  Vimal K. Kamineni ,  Randolph F. Knarr ,  Balasubramanian Pranatharthiharan ,  Muthumanickam Sankarapandian

IPC: H01L21/8234 ,  H01L21/768 ,  H01L21/28 ,  H01L29/40 ,  H01L29/66

Abstract: After forming a material stack including a gate dielectric, a work function metal and a cobalt gate electrode in a gate cavity formed by removing a sacrificial gate structure, the cobalt gate electrode is recessed by oxidizing the cobalt gate electrode to provide a cobalt oxide layer on a surface of the cobalt gate electrodes and removing the cobalt oxide layer from the surface of the cobalt gate electrodes by a chemical wet etch. The oxidation and oxide removal steps can be repeated until the cobalt gate electrode is recessed to any desired thickness. The work function metal can be recessed after the recessing of the cobalt gate electrode is completed or during the recessing of the cobalt gate electrode.

公开(公告)号：US20190096679A1

公开(公告)日：2019-03-28

申请号：US15712996

申请日：2017-09-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Balaji Kannan ,  Bala Haran ,  Vimal K. Kamineni ,  Sungkee Han ,  Neal Makela ,  Suraj K. Patil ,  Pei Liu ,  Chih-Chiang Chang ,  Katsunori Onishi ,  Keith Kwong Hon Wong ,  Ruilong Xie ,  Chanro Park ,  Min Gyu Sung

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

Abstract: Structures for a field-effect transistor and methods for forming a structure for a field-effect transistor. A gate cavity is formed in a dielectric layer that includes a bottom surface and a plurality sidewalls that extend to the bottom surface. A gate dielectric layer is formed at the sidewalls and the bottom surface of the gate cavity. A work function metal layer is deposited on the gate dielectric layer at the sidewalls and the bottom surface of the gate cavity. A fill metal layer is deposited inside the gate cavity after the work function metal layer is deposited. The fill metal layer is formed in direct contact with the work function metal layer.

公开(公告)号：US09356149B2

公开(公告)日：2016-05-31

申请号：US14795716

申请日：2015-07-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vimal K. Kamineni ,  Ruilong Xie ,  Robert Miller

IPC: H01L29/78 ,  H01L29/417 ,  H01L21/285 ,  H01L29/66 ,  H01L23/535 ,  H01L29/45 ,  H01L29/49

CPC classification number: H01L29/7851 ,  H01L21/28518 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/495 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor transistor has a structure including a semiconductor substrate, a source region, a drain region and a channel region in between the source region and the drain region. A metal gate, having a top conductive portion of tungsten is provided above the channel region. A first silicon nitride protective layer over the source region and the drain region and a second silicon nitride protective layer over the gate region are provided. The first silicon nitride protective layer and the second silicon nitride protective layer are configured to allow punch-through of the first silicon nitride protective layer while preventing etching through the second silicon nitride protective layer. Source and drain silicide is protected by avoiding fully etching a gate opening unless either the etching used would not harm the silicide, or the silicide and source and drain contacts are created prior to fully etching an opening to the gate for a gate contact.

公开(公告)号：US09117930B2

公开(公告)日：2015-08-25

申请号：US13960200

申请日：2013-08-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vimal K. Kamineni ,  Derya Deniz ,  Abner Bello ,  Abhijeet Paul ,  Robert J. Miller ,  William J. Taylor, Jr.

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0924

Abstract: One method disclosed herein includes forming a first stressed conductive layer within the trenches of a FinFET device and above the upper surface of a fin, forming a second stressed conductive layer above the first stressed conductive layer, removing a portion of the second stressed conductive layer and a portion of the first stressed conductive layer that is positioned above the fin while leaving portions of the first stressed conductive layer positioned within the trenches, and forming a conductive layer above the second stressed conductive layer, the upper surface of the fin and the portions of the first stressed conductive layer positioned within the trenches.

Abstract translation: 本文公开的一种方法包括在FinFET器件的沟槽内并在鳍的上表面上方形成第一应力导电层，在第一应力导电层上形成第二应力导电层，去除第二应力导电层的一部分， 所述第一应力导电层的位于所述鳍片上方的部分，同时留下位于所述沟槽内的所述第一应力导电层的部分，并且在所述第二应力导电层上方形成导电层，所述翅片的上表面和 第一应力导电层位于沟槽内。

公开(公告)号：US20150187896A1

公开(公告)日：2015-07-02

申请号：US14146399

申请日：2014-01-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vimal K. Kamineni ,  Ruilong Xie ,  Robert Miller

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/285

CPC classification number: H01L29/7851 ,  H01L21/28518 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/495 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor transistor has a structure including a semiconductor substrate, a source region, a drain region and a channel region in between the source region and the drain region. A metal gate, having a top conductive portion of tungsten is provided above the channel region. A first silicon nitride protective layer over the source region and the drain region and a second silicon nitride protective layer over the gate region are provided. The first silicon nitride protective layer and the second silicon nitride protective layer are configured to allow punch-through of the first silicon nitride protective layer while preventing etching through the second silicon nitride protective layer. Source and drain silicide is protected by avoiding fully etching a gate opening unless either the etching used would not harm the silicide, or the silicide and source and drain contacts are created prior to fully etching an opening to the gate for a gate contact.

Abstract translation: 半导体晶体管具有在源极区域和漏极区域之间的半导体衬底，源极区域，漏极区域和沟道区域的结构。 在通道区域的上方设置有具有钨的顶部导电部分的金属栅极。 提供了源极区域和漏极区域上的第一氮化硅保护层和栅极区域上的第二氮化硅保护层。 第一氮化硅保护层和第二氮化硅保护层被配置为允许第一氮化硅保护层的穿通，同时防止蚀刻通过第二氮化硅保护层。 通过避免完全蚀刻栅极开口来保护源极和漏极硅化物，除非所用的蚀刻不会对硅化物造成伤害，或者在完全蚀刻用于栅极接触的栅极的开口之前产生硅化物和源极和漏极接触。