公开(公告)号：US09721889B1

公开(公告)日：2017-08-01

申请号：US15219378

申请日：2016-07-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chengyu C. Niu ,  Vimal K. Kamineni ,  Mark V. Raymond ,  Xunyuan Zhang

IPC: H01L23/48 ,  H01L23/528 ,  H01L23/532 ,  H01L23/535 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76844 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53266 ,  H01L23/535

Abstract: Integrated circuit (IC) structure embodiments and methods of forming them with middle of the line (MOL) contacts that incorporate a protective cap, which provides protection from damage during back end of the line (BEOL) processing. Each MOL contact has a main body in a lower portion of a contact opening. The main body has a liner (e.g., a titanium nitride layer) that lines the lower portion and a metal layer on the liner. The MOL contact also has a protective cap in an upper portion of the contact opening above the first metal layer and extending laterally over the liner to the sidewalls of the contact opening. The protective cap has an optional liner, which is different from the liner in the lower portion, and a metal layer, which is either the same or different than the metal in the main body.

公开(公告)号：US20170148669A1

公开(公告)日：2017-05-25

申请号：US14948214

申请日：2015-11-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vimal Kamineni ,  Mark V. Raymond ,  Praneet Adusumilli ,  Chengyu Niu

IPC: H01L21/768 ,  H01L23/522 ,  H01L29/78

CPC classification number: H01L23/535 ,  H01L21/28518 ,  H01L21/31116 ,  H01L21/67207 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/53266 ,  H01L23/53295 ,  H01L29/45 ,  H01L29/78

Abstract: Methods, apparatus, and systems for fabricating a semiconductor device comprising a semiconductor substrate; an oxide layer above the semiconductor substrate; a first metal component comprising tungsten disposed within the oxide layer; an interlayer dielectric (ILD) above the oxide layer, wherein the ILD comprises a trench and a bottom of the trench comprises at least a portion of the top of the first metal component; a barrier material disposed on sidewalls and the bottom of the trench; and a second metal component disposed in the trench.

公开(公告)号：US09142633B2

公开(公告)日：2015-09-22

申请号：US13714049

申请日：2012-12-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Paul R. Besser ,  Mark V. Raymond ,  Valli Arunachalam ,  Hoon Kim

IPC: H01L21/283 ,  H01L29/49 ,  H01L21/285 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4916 ,  H01L21/28518 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate and forming fins over the semiconductor substrate. Each fin is formed with sidewalls. The method further includes conformally depositing a metal film stack on the sidewalls of each fin. In the method, the metal film stack is annealed to form a metal silicide film over the sidewalls of each fin.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，制造集成电路的方法包括提供半导体衬底并在半导体衬底上形成翅片。 每个翅片形成有侧壁。 该方法还包括在每个翅片的侧壁上共形沉积金属膜堆叠。 在该方法中，金属膜堆叠被退火以在每个翅片的侧壁上形成金属硅化物膜。

公开(公告)号：US20190386107A1

公开(公告)日：2019-12-19

申请号：US16555734

申请日：2019-08-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Hao Tang ,  Cheng Chi ,  Daniel Chanemougame ,  Lars W. Liebmann ,  Mark V. Raymond

IPC: H01L29/417 ,  H01L21/768 ,  H01L29/66 ,  H01L21/285 ,  H01L23/535 ,  H01L29/78 ,  H01L29/45

Abstract: One illustrative transistor device disclosed herein includes, among other things, a gate positioned above a semiconductor substrate, the gate comprising a gate structure, a conductive source/drain metallization structure positioned adjacent the gate, the conductive source/drain metallization structure having a front face, and an insulating spacer that is positioned on and in contact with at least a portion of the front face of the conductive source/drain metallization structure. In this example, the device also includes a gate contact opening that exposes at least a portion of the insulating spacer and a portion of an upper surface of the gate structure and a conductive gate contact structure positioned in the gate contact opening, wherein the conductive gate contact structure contacts at least a portion of the insulating spacer and wherein the conductive gate contact structure is conductively coupled to the gate structure.

公开(公告)号：US10483363B2

公开(公告)日：2019-11-19

申请号：US15581105

申请日：2017-04-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Hao Tang ,  Cheng Chi ,  Daniel Chanemougame ,  Lars W. Liebmann ,  Mark V. Raymond

IPC: H01L29/417 ,  H01L21/768 ,  H01L29/66 ,  H01L21/285 ,  H01L23/535 ,  H01L29/45 ,  H01L29/78

Abstract: One method includes forming a gate above a semiconductor substrate, the gate comprising a gate structure and a gate cap positioned above the gate structure, forming a conductive source/drain metallization structure adjacent the gate in each of the source/drain regions and forming a recess in each of the conductive source/drain metallization structures. The method further includes forming a spacer structure that comprises recess filling portions that substantially fill the recesses and a portion that extends across the gate cap, wherein a portion of the gate cap is exposed within the spacer structure, forming an insulating material within the spacer structure and on the exposed portion of the gate cap, forming a gate contact opening that exposes a portion of an upper surface of the gate structure and forming a conductive gate contact structure (CB) in the conductive gate contact opening.

公开(公告)号：US10283372B2

公开(公告)日：2019-05-07

申请号：US15705956

申请日：2017-09-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sean Xuan Lin ,  Xunyuan Zhang ,  Mark V. Raymond ,  Errol Todd Ryan ,  Nicholas V. LiCausi

IPC: H01L27/10 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/532

Abstract: Methods of forming interconnects. An interconnect opening is formed in a dielectric layer. A first conductor layer composed of a first metal is formed in the interconnect opening. A second conductor layer is formed inside the interconnect opening by displacing the first metal of the first conductor layer and replacing the first metal with a second metal different from the first metal.

公开(公告)号：US10157794B1

公开(公告)日：2018-12-18

申请号：US15626321

申请日：2017-06-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Puneet H. Suvarna ,  Steven Bentley ,  Mark V. Raymond ,  Peter M. Zeitzoff

IPC: H01L21/8234 ,  H01L21/285 ,  H01L27/088 ,  H01L29/45 ,  H01L29/78 ,  H01L29/08 ,  H01L29/423

Abstract: Embodiments of the disclosure provide integrated circuit (IC) structures with stepped epitaxial regions and methods of forming the same. A method according to the disclosure can include: removing a portion of a substrate to form a recess therein, the portion of the substrate being laterally adjacent to a semiconductor fin having a sidewall spacer thereon, to expose an underlying sidewall of the semiconductor fin; forming an epitaxial layer within the recess, such that the epitaxial layer laterally abuts the sidewall of the semiconductor fin below the sidewall spacer; removing a portion of the epitaxial layer to form a stepped epitaxial region adjacent to the semiconductor fin, the stepped epitaxial region including a first region laterally abutting the sidewall of the semiconductor fin, and a second region laterally adjacent to the first region; and forming a gate structure over the stepped epitaxial region and adjacent to the semiconductor fin.

公开(公告)号：US20180308752A1

公开(公告)日：2018-10-25

申请号：US15494762

申请日：2017-04-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Frank W. Mont ,  Sean X. Lin ,  Mark V. Raymond

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/535 ,  H01L23/528

CPC classification number: H01L21/76895 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76883 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53242 ,  H01L23/535

Abstract: Interconnect structures and methods of forming interconnect structures. An opening is formed that penetrates from a top surface of a dielectric layer into the dielectric layer. A first conductor layer is conformally deposited with a uniform thickness on the dielectric layer surrounding the first opening. A second conductor layer is formed in a space inside the first opening that is interior of the first conductor layer. The first conductor layer and the second conductor layer collectively define a hybrid feature that is embedded in the dielectric layer.

公开(公告)号：US09859217B1

公开(公告)日：2018-01-02

申请号：US15614925

申请日：2017-06-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chengyu C. Niu ,  Vimal K. Kamineni ,  Mark V. Raymond ,  Xunyuan Zhang

IPC: H01L21/44 ,  H01L23/528 ,  H01L23/532 ,  H01L23/535 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76844 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53266 ,  H01L23/535

Abstract: Integrated circuit (IC) structure embodiments and methods of forming them with middle of the line (MOL) contacts that incorporate a protective cap, which provides protection from damage during back end of the line (BEOL) processing. Each MOL contact has a main body in a lower portion of a contact opening. The main body has a liner (e.g., a titanium nitride layer) that lines the lower portion and a metal layer on the liner. The MOL contact also has a protective cap in an upper portion of the contact opening above the first metal layer and extending laterally over the liner to the sidewalls of the contact opening. The protective cap has an optional liner, which is different from the liner in the lower portion, and a metal layer, which is either the same or different than the metal in the main body.