公开(公告)号：US20240063315A1

公开(公告)日：2024-02-22

申请号：US17820979

申请日：2022-08-19

Applicant: GlobalFoundries U.S. Inc.

Inventor： Siva P. Adusumilli ,  Ramsey Hazbun ,  John J. Ellis-Monaghan ,  Rajendran Krishnasamy

IPC: H01L31/0232 ,  H01L31/028 ,  H01L31/105 ,  H01L31/18

CPC classification number: H01L31/02327 ,  H01L31/028 ,  H01L31/105 ,  H01L31/1808

Abstract: A photodetector structure includes a first semiconductor material layer over a doped well in a substrate. The photodetector structure includes an air gap vertically between the first semiconductor material layer and a first portion of the doped well. The photodetector structure includes an insulative collar on the first portion of the doped well and laterally surrounding the air gap. The photodetector structure may include a second semiconductor material layer on the first portion of the doped well and laterally surrounded by the insulative collar. The photodetector structure may include a third semiconductor layer over the first semiconductor layer.

公开(公告)号：US20230402447A1

公开(公告)日：2023-12-14

申请号：US17806797

申请日：2022-06-14

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anindya Nath ,  Alain F. Loiseau ,  Rajendran Krishnasamy ,  Souvick Mitra

IPC: H01L27/02 ,  H01L29/87

CPC classification number: H01L27/0248 ,  H01L29/87

Abstract: Disclosed are a structure and method. The structure includes a substrate having monocrystalline lower and upper portions and a high resistance portion (e.g., a trap-rich amorphous portion) between the lower and upper portions. An isolation region extends through the upper portion, is above the high resistance portion, and is positioned laterally adjacent to a device section of the upper portion also above the high resistance portion. One or more devices (e.g., a diode, multiple diodes, a diode string, multiple diode strings, etc.) are on the trench isolation region, on the device section, and/or within the device section. The device(s) are separated from the lower portion by the high resistance portion and, potentially, by the isolation region or the device section. Such device(s) can be employed for electrostatic discharge (ESD) protection on RFIC chips and can sustain a larger RF voltage, provide area savings, reduce parasitic capacitance, improve harmonics, etc.

公开(公告)号：US20230395714A1

公开(公告)日：2023-12-07

申请号：US17831496

申请日：2022-06-03

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anindya Nath ,  Alain Loiseau ,  Rajendran Krishnasamy

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/7835 ,  H01L21/823892 ,  H01L29/66659

Abstract: Device structures with an isolation well and methods of forming a device structure with an isolation well. The structure comprises a first well of a first conductivity type in a semiconductor substrate, and a second well of a second conductivity type in the semiconductor substrate. The second conductivity type is opposite to the first conductivity type. The first well includes a plurality of segments, and the second well is positioned in a vertical direction between the segments of the first well and a top surface of the semiconductor substrate.

公开(公告)号：US20230317776A1

公开(公告)日：2023-10-05

申请号：US17708561

申请日：2022-03-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Michel Abou-Khalil ,  Steven M. Shank ,  Aaron Vallett ,  Sarah McTaggart ,  Rajendran Krishnasamy

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/0649 ,  H01L29/4236 ,  H01L29/1087

Abstract: Semiconductor structures including electrical isolation and methods of forming a semiconductor structure including electrical isolation. The structure includes a semiconductor substrate having a first surface, a recess in the first surface, and a second surface inside the first recess. The structure further includes a shallow trench isolation region extending from the first surface into the semiconductor substrate. The shallow trench isolation region is positioned to surround an active device region including the recess. A field-effect transistor includes a gate electrode positioned on a portion of the second surface.

公开(公告)号：US20230268394A1

公开(公告)日：2023-08-24

申请号：US17679166

申请日：2022-02-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sarah A. McTaggart ,  Rajendran Krishnasamy ,  Qizhi Liu

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/732 ,  H01L29/737 ,  H01L21/265

CPC classification number: H01L29/0817 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7371 ,  H01L21/26586

Abstract: Disclosed are a structure including a transistor and a method of forming the structure. The transistor includes an emitter region with first and second emitter portions. The first emitter portion extends through a dielectric layer. The second emitter portion is on the first emitter portion and the top of the dielectric layer. An additional dielectric layer covers the top of the second emitter portion. The second emitter portion and the dielectric and additional dielectric layers are wider than the first emitter portion. At least a section of the second emitter portion is narrower than the dielectric and additional dielectric layers, thereby creating cavities positioned vertically between edge portions of the dielectric and additional dielectric layers and positioned laterally adjacent to the second emitter portion. The cavities are filled with dielectric material or dielectric material blocks the side openings to the cavities creating pockets of air, of gas or under vacuum.

公开(公告)号：US12166476B2

公开(公告)日：2024-12-10

申请号：US18065768

申请日：2022-12-14

Applicant: GlobalFoundries U.S. Inc.

Inventor： Santosh Sharma ,  Johnatan Avraham Kantarovsky ,  Rajendran Krishnasamy

IPC: H03K17/08 ,  H01L29/40 ,  H01L29/78

Abstract: An integrated circuit (IC) having a high voltage semiconductor device with a plurality of field plates between the gate and drain. The IC further includes a biasing circuit electrically coupled to each of the plurality of field plates, the biasing circuit including a plurality of high voltage depletion mode transistors, each having a pinch off voltage. The high voltage depletion mode transistors may have different pinch off voltages, and each of the field plates are each independently biased by a different one of the high voltage depletion mode transistors.

公开(公告)号：US12154956B1

公开(公告)日：2024-11-26

申请号：US18632902

申请日：2024-04-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Johnatan Avraham Kantarovsky ,  Rajendran Krishnasamy ,  Mark D. Levy ,  John J. Ellis-Monaghan ,  Michael J. Zierak ,  Kristin Marie Welch

IPC: H01L29/51 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

Abstract: Disclosed are a structure with a multi-level field plate and a method of forming the structure. The field plate includes multiple first conductors on a dielectric layer and separated from each other by spaces with different widths (e.g., by with progressively decreasing widths). A conformal additional dielectric layer extends over the first conductors and onto the dielectric layer within the spaces. The field plate also includes, on the additional dielectric layer, second conductor(s) with portions thereof extending into the spaces. Within the spaces, the second conductor portions are at different heights (e.g., at progressively increasing heights) above the dielectric layer. Such a field plate can be incorporated into a transistor (e.g., a high electron mobility transistor (HEMT)) to, not only reduce the peak of an electric field exhibited proximal to a gate terminal, but to ensure the electric field is essentially uniform level between the gate and drain terminals.

公开(公告)号：US20240290776A1

公开(公告)日：2024-08-29

申请号：US18173313

申请日：2023-02-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anindya Nath ,  Rajendran Krishnasamy ,  Robert J. Gauthier, JR.

IPC: H01L27/02 ,  H01L29/87

CPC classification number: H01L27/0262 ,  H01L29/87

Abstract: Embodiments of the disclosure provide a structure including a semiconductor substrate. The semiconductor substrate includes a porous semiconductor region, the porous semiconductor region including a cavity. The cavity includes a semiconductor layer therein. The porous semiconductor further includes a device. The device includes a first well at least partially in the semiconductor layer and a second well at least partially in the semiconductor layer and positioned laterally immediately adjacent the first well. The device further includes a first doped region abutting the first well; and a second doped region abutting the second well, wherein the first well and the second doped region have a first type conductivity and the second well and the first doped region having a second type conductivity that is different from the first type conductivity.

公开(公告)号：US20240250120A1

公开(公告)日：2024-07-25

申请号：US18157939

申请日：2023-01-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani Pandey ,  Rajendran Krishnasamy

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/311 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0642 ,  H01L21/02203 ,  H01L21/31111 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7833

Abstract: Disclosed are embodiments of a semiconductor structure including a semiconductor device with an active device region and, within the active device region, porous semiconductor material adjacent to an isolation structure. In some embodiments, the semiconductor device can be a laterally diffused metal oxide semiconductor field effect transistor (LDMOSFET). The LDMOSFET can include an active device region, a well region within the active device region and, within the well region, an isolation structure, a porous region immediately adjacent to the isolation structure, and a drain drift region that borders the isolation structure (e.g., between a channel region and a drain region). The porous region can modify the electric field in the drain drift region around the isolation structure and, as a result, can improve both drain-to-source breakdown voltage (BVdss) and transconductance (Gm) of the device. Also disclosed are method embodiments for forming the semiconductor structure.

公开(公告)号：US20240213240A1

公开(公告)日：2024-06-27

申请号：US18086938

申请日：2022-12-22

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sagar Premnath Karalkar ,  Ephrem Gebreselasie ,  Rajendran Krishnasamy ,  Robert J. Gauthier, JR. ,  Souvick Mitra

IPC: H01L27/02

CPC classification number: H01L27/0262 ,  H01L21/76224

Abstract: Structures for an electrostatic discharge protection device and methods of forming same. The structure comprises a first well and a second well in the semiconductor substrate. The first and second wells have a first conductivity type. The structure further comprises a third well and a fourth well in the semiconductor substrate. The third and fourth wells have a second conductivity type, the third well includes a portion that overlaps with the first well, and the fourth well includes a portion that overlaps with the second well.