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    OPTICAL WAVEGUIDE WITH STACKED CLADDING MATERIAL LAYERS
    22.
    发明公开
    OPTICAL WAVEGUIDE WITH STACKED CLADDING MATERIAL LAYERS 审中-公开

    公开(公告)号：US20230266526A1

    公开(公告)日：2023-08-24

    申请号：US17674905

    申请日：2022-02-18

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Shesh Mani Pandey ,  Yusheng Bian ,  Francis O. Afzal

    IPC: G02B6/028 ,  G02B6/036

    CPC classification number: G02B6/0288 ,  G02B6/036

    Abstract: Disclosed is an optical waveguide including a waveguide core and waveguide cladding surrounding the waveguide core. The waveguide cladding includes at least one stack of cladding material layers positioned laterally adjacent to a sidewall of the waveguide core such that each cladding material layer in the stack abuts the sidewall of the waveguide core. Each of the cladding material layers in the stack has a smaller refractive index than the waveguide core and at least two of the cladding material layers in the stack have different refractive indices, thereby tailoring field confinement and reshaping the optical mode. Different embodiments include different numbers of cladding material layers in the stack, different stacking orders of the cladding material layers, different waveguide core types, symmetric or asymmetric cladding structures on opposite sides of the waveguide core, etc. Also disclosed is a method of forming the optical waveguide.

    LATERAL BIPOLAR JUNCTION TRANSISTORS WITH A BACK-GATE
    23.
    发明申请
    LATERAL BIPOLAR JUNCTION TRANSISTORS WITH A BACK-GATE 有权

    公开(公告)号：US20230112235A1

    公开(公告)日：2023-04-13

    申请号：US17692517

    申请日：2022-03-11

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Hong Yu ,  Shesh Mani Pandey

    IPC: H01L29/10 ,  H01L29/66 ,  H01L29/735

    Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a substrate having a well, a first terminal including a first raised semiconductor layer, a second terminal including a second raised semiconductor layer, and a base layer positioned in a lateral direction between the first raised semiconductor layer of the first terminal and the second raised semiconductor layer of the second terminal. The base layer has an overlapping arrangement with the well. The structure further includes a dielectric layer positioned in a vertical direction between the first terminal and the substrate, the second terminal and the substrate, and the base layer and the substrate.

    Transistor comprising an air gap positioned adjacent a gate electrode
    25.
    发明授权
    Transistor comprising an air gap positioned adjacent a gate electrode 有权

    公开(公告)号：US11456382B2

    公开(公告)日：2022-09-27

    申请号：US16664056

    申请日：2019-10-25

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Laertis Economikos ,  Shesh Mani Pandey ,  Hui Zang ,  Haiting Wang ,  Jinping Liu

    IPC: H01L29/49 ,  H01L29/423 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66

    Abstract: A transistor device disclosed herein includes, among other things, a gate electrode positioned above a semiconductor material region, a sidewall spacer positioned adjacent the gate electrode, a gate insulation layer having a first portion positioned between the gate electrode and the semiconductor material region and a second portion positioned between a lower portion of the sidewall spacer and the gate electrode along a portion of a sidewall of the gate electrode, an air gap cavity located between the sidewall spacer and the gate electrode and above the second portion of the gate insulation layer, and a gate cap layer positioned above the gate electrode, wherein the gate cap layer seals an upper end of the air gap cavity so as to define an air gap positioned adjacent the gate electrode.

    SEMICONDUCTOR DEVICE INCLUDING POROUS SEMICONDUCTOR MATERIAL ADJACENT AN ISOLATION STRUCTURE
    27.
    发明公开
    SEMICONDUCTOR DEVICE INCLUDING POROUS SEMICONDUCTOR MATERIAL ADJACENT AN ISOLATION STRUCTURE 审中-公开

    公开(公告)号：US20240250120A1

    公开(公告)日：2024-07-25

    申请号：US18157939

    申请日：2023-01-23

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Shesh Mani Pandey ,  Rajendran Krishnasamy

    IPC: H01L29/06 ,  H01L21/02 ,  H01L21/311 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/0642 ,  H01L21/02203 ,  H01L21/31111 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7833

    Abstract: Disclosed are embodiments of a semiconductor structure including a semiconductor device with an active device region and, within the active device region, porous semiconductor material adjacent to an isolation structure. In some embodiments, the semiconductor device can be a laterally diffused metal oxide semiconductor field effect transistor (LDMOSFET). The LDMOSFET can include an active device region, a well region within the active device region and, within the well region, an isolation structure, a porous region immediately adjacent to the isolation structure, and a drain drift region that borders the isolation structure (e.g., between a channel region and a drain region). The porous region can modify the electric field in the drain drift region around the isolation structure and, as a result, can improve both drain-to-source breakdown voltage (BVdss) and transconductance (Gm) of the device. Also disclosed are method embodiments for forming the semiconductor structure.

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