公开(公告)号：US20220189877A1

公开(公告)日：2022-06-16

申请号：US17121810

申请日：2020-12-15

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  Vibhor Jain ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  John J. Pekarik

IPC: H01L23/532 ,  H01L23/48 ,  H01L23/522 ,  H01L21/768 ,  H01L23/00 ,  H01L23/373

Abstract: Processing forms an integrated circuit structure having first and second layers on opposite sides of an insulator, and an interconnect structure extending through the insulator between the first layer and the second layer. The interconnect structure is formed in an opening extending through the insulator between the first layer and the second layer and has an electrical conductor in the opening extending between the first layer and the second layer and a thermally conductive electrical insulator liner along sidewalls of the opening extending between the first layer and the second layer. The electrical conductor is positioned to conduct electrical signals between the first layer and the second layer, and the thermally conductive electrical insulator liner is positioned to transfer heat between the first layer and the second layer.

公开(公告)号：US11355409B2

公开(公告)日：2022-06-07

申请号：US16405325

申请日：2019-05-07

Applicant: GlobalFoundries U.S. Inc.

Inventor： Hanyi Ding ,  Vibhor Jain ,  Alvin J. Joseph ,  Anthony K. Stamper

IPC: H01L29/66 ,  H01L23/367 ,  H01L29/08 ,  H01L21/48 ,  H01L29/417 ,  H01L29/732

Abstract: Chip packages and methods of forming a chip package. The chip package includes a power amplifier and a thermal pathway structure configured to influence transport of heat energy. The power amplifier includes a first emitter finger and a second emitter finger having at least one parameter that is selected based upon proximity to the thermal pathway structure.

公开(公告)号：US11094834B2

公开(公告)日：2021-08-17

申请号：US16790084

申请日：2020-02-13

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Qizhi Liu ,  Vibhor Jain ,  John J. Pekarik ,  Judson R. Holt

IPC: H01L21/00 ,  H01L29/808 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L21/02 ,  H01L21/225 ,  H01L29/66

Abstract: A junction field effect transistor (JFET) structure includes a doped polysilicon gate over a channel region of a semiconductor layer. The doped polysilicon gate has a first doping type. A raised epitaxial source is on the source region of the semiconductor layer and adjacent a first sidewall of the doped polysilicon gate, and has a second doping type opposite the first doping type. A raised epitaxial drain is on the drain region of the semiconductor layer and adjacent a second sidewall of the doped polysilicon gate, and has the second doping type. A doped semiconductor region is within the channel region of the semiconductor layer and extending from the source region to the drain region, and a non-conductive portion of the semiconductor layer is within the channel region to separate the doped semiconductor region from the doped polysilicon gate.

公开(公告)号：US10964796B2

公开(公告)日：2021-03-30

申请号：US15427182

申请日：2017-02-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  Vibhor Jain ,  Renata A. Camillo-Castillo

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L29/10 ,  H01L29/737 ,  H01L21/762 ,  H01L29/732

Abstract: According to a semiconductor device herein, the device includes a substrate. An active device is formed in the substrate. The active device includes a collector region, a base region formed on the collector region, and an emitter region formed on the base region. An isolation structure is formed in the substrate around the active device. A trench filled with a compressive material is formed in the substrate and positioned laterally adjacent to the emitter region and base region. The trench extends at least partially into the base region.

公开(公告)号：US20210091213A1

公开(公告)日：2021-03-25

申请号：US16748055

申请日：2020-01-21

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  John J. Pekarik ,  Qizhi Liu ,  Judson Holt

IPC: H01L29/737 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A collector layer includes an inclined side surface, and a dielectric layer is positioned in a lateral direction adjacent to the inclined side surface of the collector layer. An intrinsic base is disposed over the collector layer, and an emitter is disposed over the intrinsic base. An airgap is positioned between the dielectric layer and the inclined side surface of the collector layer in the lateral direction, and an extrinsic base is positioned in the lateral direction adjacent to the intrinsic base. The extrinsic base is positioned over the airgap.

公开(公告)号：US12170313B2

公开(公告)日：2024-12-17

申请号：US18324637

申请日：2023-05-26

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  Anthony K. Stamper ,  John J. Ellis-Monaghan ,  Steven M. Shank ,  Rajendran Krishnasamy

IPC: H01L29/06 ,  H01L21/763 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66 ,  H01L29/737

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a trap rich isolation region embedded within the bulk substrate; and a heterojunction bipolar transistor above the trap rich isolation region, with its sub-collector region separated by the trap rich isolation region by a layer of the bulk substrate.

公开(公告)号：US12159926B2

公开(公告)日：2024-12-03

申请号：US18373598

申请日：2023-09-27

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Haiting Wang ,  Alexander Derrickson ,  Jagar Singh ,  Vibhor Jain ,  Andreas Knorr ,  Alexander Martin ,  Judson R. Holt ,  Zhenyu Hu

IPC: H01L29/735 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/737

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. A structure includes: an intrinsic base comprising semiconductor material in a channel region of a semiconductor substrate; an extrinsic base vertically above the intrinsic base; a raised collector region on the semiconductor substrate and laterally connected to the intrinsic base; and a raised emitter region on the semiconductor substate and laterally connected to the intrinsic base.

公开(公告)号：US12046633B2

公开(公告)日：2024-07-23

申请号：US17157269

申请日：2021-01-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Mark D. Levy ,  Siva P. Adusumilli ,  Johnatan A. Kantarovsky ,  Vibhor Jain

IPC: H01L29/06 ,  H01L21/308 ,  H01L21/764 ,  H01L27/06 ,  H01L27/07 ,  H01L29/08

CPC classification number: H01L29/0657 ,  H01L21/308 ,  H01L21/764 ,  H01L27/0635 ,  H01L27/0755 ,  H01L29/0653 ,  H01L29/0821

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to airgap structures in a doped region under one or more transistors and methods of manufacture. The structure includes: a semiconductor material comprising a doped region; one or more sealed airgap structures breaking up the doped region of the semiconductor material; and a field effect transistor over the one or more sealed airgap structures and the semiconductor material.

公开(公告)号：US12027553B2

公开(公告)日：2024-07-02

申请号：US17896401

申请日：2022-08-26

Applicant: GlobalFoundries U.S. Inc.

Inventor： Siva P. Adusumilli ,  Vibhor Jain ,  Alvin J. Joseph ,  Steven M. Shank

IPC: H01L27/146

CPC classification number: H01L27/14629 ,  H01L27/1462 ,  H01L27/1463 ,  H01L27/14685

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodetectors with buried airgap mirror reflectors. The structure includes a photodetector and at least one airgap in a substrate under the photodetector.

公开(公告)号：US20240172455A1

公开(公告)日：2024-05-23

申请号：US17990800

申请日：2022-11-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： John J. Pekarik ,  Hong Yu ,  Vibhor Jain ,  Alexander Derrickson ,  Venkatesh Gopinath

IPC: H01L47/00 ,  H01L29/66 ,  H01L29/737

CPC classification number: H01L27/2445 ,  H01L29/66242 ,  H01L29/7371 ,  H01L45/1233 ,  H01L45/16

Abstract: Structures that include bipolar junction transistors and methods of forming such structures. The structure comprises a substrate having a top surface, a trench isolation region in the substrate, and a base layer on the top surface of the substrate. The base layer extending across the trench isolation region. A first bipolar junction transistor includes a first collector in the substrate and a first emitter on a first portion of the first base layer. The first portion of the first base layer is positioned between the first collector and the first emitter. A second bipolar junction transistor includes a second collector in the substrate and a second emitter on a second portion of the first base layer. The second portion of the first base layer is positioned between the second collector and the second emitter.