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公开(公告)号：US5525261A
公开(公告)日：1996-06-11
申请号：US324823
申请日：1994-10-18
CPC分类号： H05F1/00 , Y10S57/901 , Y10T428/31507 , Y10T428/31511 , Y10T428/31551 , Y10T428/31725 , Y10T428/31739 , Y10T428/31786 , Y10T442/2434
摘要： Antistatic agents and their use in natural or synthetic textiles or formed plastic substrates to enhance the surface resistivity thereof. The antistatic agent comprises a mixture of polyoxyalkylamine derivatives comprising a fluoro-acid moiety, a fatty acid moiety and a quaternary ammonium moiety. The coatings remain effective after exposure of the treated substrate to an aqueous environment and to elevated temperatures.
摘要翻译： 抗静电剂及其在天然或合成纺织品或成形塑料基材中的用途，以增强其表面电阻率。 抗静电剂包括含氟酸部分，脂肪酸部分和季铵部分的聚氧烷基胺衍生物的混合物。 在将处理的基底暴露于水性环境和升高的温度之后，涂层保持有效。
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公开(公告)号：US5382324A
公开(公告)日：1995-01-17
申请号：US68447
申请日：1993-05-27
摘要： Method for enhancing the strength of paper comprising the steps ofA) contacting paper fibers with a water slurry of at least one polymer which is a homopolymer and/or a random copolymer of an allylamine;B) forming a paper sheet from the paper fibers; andC) drying the paper sheet.
摘要翻译： 提高纸张强度的方法，包括以下步骤：A）使纸纤维与至少一种作为烯丙胺的均聚物和/或无规共聚物的聚合物的水浆料接触; B）从纸纤维形成纸片; 和C）干燥纸张。
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公开(公告)号：US5350796A
公开(公告)日：1994-09-27
申请号：US142642
申请日：1993-10-25
摘要： A composition for improving the wet strength of cellulosic fibrous webs is comprised of an aminopolyamide-epichlorohydrin acid salt resin having an E/N ratio of from about 0.6 to about 2.0 and from about 1% to about 35% of a water soluble cationic polymer based on the weight of the resin. The composition has a total organic chlorine content of from about 0.5% to 1.0% by weight based on the weight of the aminopolyamide-epichlorohydrin acid salt resin.
摘要翻译： 用于改善纤维素纤维网的湿强度的组合物由具有约0.6至约2.0的E / N比和约1％至约35％的水溶性阳离子聚合物基的氨基多胺 - 表氯醇酸盐树脂 关于树脂的重量。 该组合物的总有机氯含量为氨基聚酰胺 - 表氯醇酸盐树脂重量的约0.5％至1.0％。
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公开(公告)号：US20160098075A1
公开(公告)日：2016-04-07
申请号：US14966708
申请日：2015-12-11
申请人： Sanjeev Jahagirdar , Varghese George , John B. Conrad , Robert Milstrey , Stephen A. Fischer , Alon Naveh , Shai Rotem
发明人： Sanjeev Jahagirdar , Varghese George , John B. Conrad , Robert Milstrey , Stephen A. Fischer , Alon Naveh , Shai Rotem
CPC分类号： G06F1/3287 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3246 , G06F1/3275 , G06F1/3293 , G06F1/3296 , G06F9/4418 , G06F11/1441 , G06F12/084 , G06F12/0875 , G06F2212/281 , G06F2212/305 , G06F2212/314 , G11C7/1072 , Y02B70/123 , Y02B70/126 , Y02B70/32 , Y02D10/152 , Y02D10/172 , Y02D50/20 , Y02P80/11 , Y10T307/305 , Y10T307/406 , Y10T307/582 , Y10T307/826
摘要： Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
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公开(公告)号：US20140123286A1
公开(公告)日：2014-05-01
申请号：US13799663
申请日：2013-03-13
IPC分类号： G06F21/56
CPC分类号： G06F21/552 , G06F9/30145 , G06F21/566 , G06F2221/034
摘要： In one embodiment, a processor includes at least one execution unit and Return Oriented Programming (ROP) detection logic. The ROP detection logic may determine a ROP metric based on a plurality of control transfer events. The ROP detection logic may also determine whether the ROP metric exceeds a threshold. The ROP detection logic may also, in response to a determination that the ROP metric exceeds the threshold, provide a ROP attack notification.
摘要翻译： 在一个实施例中，处理器包括至少一个执行单元和返回定向编程（ROP）检测逻辑。 ROP检测逻辑可以基于多个控制传送事件来确定ROP度量。 ROP检测逻辑还可以确定ROP度量是否超过阈值。 ROP检测逻辑还可以响应于ROP度量超过阈值的确定，提供ROP攻击通知。
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公开(公告)号：US08230203B2
公开(公告)日：2012-07-24
申请号：US11694344
申请日：2007-03-30
申请人： Gilbert Neiger , Randolph L. Campbell , James B. Crossland , Gideon Gerzon , Leena K. Puthiyedath , Stephen A. Fischer , Steven M. Bennett , Andrew V. Anderson
发明人： Gilbert Neiger , Randolph L. Campbell , James B. Crossland , Gideon Gerzon , Leena K. Puthiyedath , Stephen A. Fischer , Steven M. Bennett , Andrew V. Anderson
CPC分类号： G06F9/45533
摘要： Embodiments of apparatuses, methods, and systems detecting spin loops in a virtual machine environment are disclosed. In one embodiment, an apparatus includes detection logic and virtualization logic. The detection logic is to detect whether a guest is executing a spin loop. The virtualization logic is to transfer control of the apparatus from the guest to a host in response to the detection logic detecting that the guest is executing the spin loop.
摘要翻译： 公开了在虚拟机环境中检测自旋回路的装置，方法和系统的实施例。 在一个实施例中，装置包括检测逻辑和虚拟逻辑。 检测逻辑是检测访客是否正在执行自旋循环。 响应于检测到客户正在执行自旋回路的检测逻辑，虚拟化逻辑是将设备的控制从客户转移到主机。
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27.发明授权Method and system for accessing memory in parallel computing using load fencing instructions 有权使用负载击剑指令并行计算访问存储器的方法和系统公开(公告)号：US08171261B2
公开(公告)日：2012-05-01
申请号：US10654573
申请日：2003-09-02
CPC分类号： G06F9/3836 , G06F9/30043 , G06F9/30047 , G06F9/30087 , G06F9/3012 , G06F9/30145 , G06F9/3808 , G06F9/3812 , G06F9/3834 , G06F9/3855 , G06F9/3857 , G06F9/3867 , G06F2009/45583 , G06F2009/45591
摘要： A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.
摘要翻译： 一种用于防止内存访问的系统和方法。 存储器负载可以围栏，或者所有内存访问都可以被围起来。 系统接收一个将内存访问指令分为较早访问和较新访问的防护指令。 存储器排序单元内的缓冲器被分配给该指令。 比栅栏指令更新的访问指令被停止。 旧的访问指令已逐渐退出。 当所有较旧的内存访问都已停用时，从缓冲区中分派防护指令。
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公开(公告)号：US20100146311A1
公开(公告)日：2010-06-10
申请号：US12706631
申请日：2010-02-16
申请人： Sanjeev Jahagirdar , Varghese George , John B. Conrad , Robert Milstrey , Stephen A. Fischer , Alon Naveh , Shai Rotem
发明人： Sanjeev Jahagirdar , Varghese George , John B. Conrad , Robert Milstrey , Stephen A. Fischer , Alon Naveh , Shai Rotem
IPC分类号： G06F1/00
CPC分类号： G06F1/3287 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3246 , G06F1/3275 , G06F1/3293 , G06F1/3296 , G06F9/4418 , G06F11/1441 , G06F12/084 , G06F12/0875 , G06F2212/281 , G06F2212/305 , G06F2212/314 , G11C7/1072 , Y02B70/123 , Y02B70/126 , Y02B70/32 , Y02D10/152 , Y02D10/172 , Y02D50/20 , Y02P80/11 , Y10T307/305 , Y10T307/406 , Y10T307/582 , Y10T307/826
摘要： Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
摘要翻译： 本发明的实施例涉及一种用于零电压处理器睡眠状态的方法和装置。 处理器可以包括专用高速缓存存储器。 电压调节器可以耦合到处理器以向处理器提供工作电压。 在处理器转换到零电压电源管理状态期间，电压调节器施加到处理器的工作电压可以减小到大约零，并且与处理器相关联的状态变量可以被保存到专用高速缓冲存储器。
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公开(公告)号：US06898700B2
公开(公告)日：2005-05-24
申请号：US09053398
申请日：1998-03-31
申请人： William C. Alexander, III , Shreekant S. Thakkar , Patrice L. Roussel , Thomas Huff , Bryant E. Bigbee , Stephen A. Fischer
发明人： William C. Alexander, III , Shreekant S. Thakkar , Patrice L. Roussel , Thomas Huff , Bryant E. Bigbee , Stephen A. Fischer
CPC分类号： G06F9/30043 , G06F9/462
摘要： The present invention discloses a method and apparatus for saving and restoring registers. A single instruction is decoded. The single instruction moves contents of a plurality of registers associated with a functional unit in a processor to a memory; the processor operates under a plurality of operational modes and operand sizes. The single instruction arranges the contents in the memory according to a predetermined format into a plurality of groups, each group is aligned at an address boundary which corresponds to a multiple of 2N bytes. The predetermined format is constant for the plurality of operational modes and operand sizes. The single instruction retains the contents of the plurality of registers after moving.
摘要翻译： 本发明公开了一种保存和恢复寄存器的方法和装置。 单个指令被解码。 单个指令将与处理器中的功能单元相关联的多个寄存器的内容移动到存储器; 处理器在多种操作模式和操作数大小下工作。 单个指令根据预定格式将内容排列到多个组中，每组在对应于2×N个字节的倍数的地址边界对齐。 对于多个操作模式和操作数大小，预定格式是恒定的。 单指令在移动后保留多个寄存器的内容。
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30.发明授权公开(公告)号：US06678810B1
公开(公告)日：2004-01-13
申请号：US09475363
申请日：1999-12-30
IPC分类号： G06F1300
CPC分类号： G06F9/3836 , G06F9/30043 , G06F9/30047 , G06F9/30087 , G06F9/3012 , G06F9/30145 , G06F9/3808 , G06F9/3812 , G06F9/3834 , G06F9/3855 , G06F9/3857 , G06F9/3867 , G06F2009/45583 , G06F2009/45591
摘要： A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.
摘要翻译： 一种用于防止内存访问的系统和方法。 存储器负载可以围栏，或者所有内存访问都可以被围起来。 系统接收一个将内存访问指令分为较早访问和较新访问的防护指令。 存储器排序单元内的缓冲器被分配给该指令。 比栅栏指令更新的访问指令会停止。 旧的访问指令已逐渐退出。 当所有较旧的内存访问都已停用时，从缓冲区中分派防护指令。
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