公开(公告)号：US10121711B2

公开(公告)日：2018-11-06

申请号：US14816708

申请日：2015-08-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sipeng Gu ,  Xiang Hu ,  Alok Vaid ,  Lokesh Subramany ,  Akshey Sehgal

IPC: H01L29/10 ,  H01L29/76 ,  H01L21/82 ,  H01L21/66 ,  G01R31/26 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092

Abstract: Approaches for providing a substrate having a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. Specifically, the FinFET device comprises a finned substrate, and a planar metrology pad formed on the substrate adjacent the fins in a metrology measurement area of the FinFET device. Processing steps include forming a first hardmask over the substrate, forming a photoresist over a portion of the first hardmask in the metrology measurement area of the FinFET device, removing the first hardmask in an area adjacent the metrology measurement area remaining exposed following formation of the photoresist, patterning a set of openings in the substrate to form the set of fins in the FinFET device in the area adjacent the metrology measurement area, depositing an oxide layer over the FinFET device, and planarizing the FinFET device to form the planar metrology pad in the metrology measurement area.

公开(公告)号：US20150340296A1

公开(公告)日：2015-11-26

申请号：US14816708

申请日：2015-08-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sipeng Gu ,  Xiang Hu ,  Alok Vaid ,  Lokesh Subramany ,  Akshey Sehgal

IPC: H01L21/66 ,  H01L27/088

CPC classification number: H01L22/30 ,  G01R31/2621 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924

Abstract: Approaches for providing a substrate having a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. Specifically, the FinFET device comprises a finned substrate, and a planar metrology pad formed on the substrate adjacent the fins in a metrology measurement area of the FinFET device. Processing steps include forming a first hardmask over the substrate, forming a photoresist over a portion of the first hardmask in the metrology measurement area of the FinFET device, removing the first hardmask in an area adjacent the metrology measurement area remaining exposed following formation of the photoresist, patterning a set of openings in the substrate to form the set of fins in the FinFET device in the area adjacent the metrology measurement area, depositing an oxide layer over the FinFET device, and planarizing the FinFET device to form the planar metrology pad in the metrology measurement area.

Abstract translation: 公开了一种用于提供具有与翅片场效应晶体管（FinFET）器件的一组翅片相邻的平面度量垫的衬底的方法。 具体地说，FinFET器件包括鳍式衬底和在FinFET器件的度量测量区域中与衬底相邻的衬底上形成的平面度量垫。 处理步骤包括在衬底上形成第一硬掩模，在FinFET器件的测量测量区域中的第一硬掩模的一部分上形成光致抗蚀剂，在形成光致抗蚀剂之后，在与测量测量区域相邻的区域中残留的部分去除第一硬掩模 在衬底中图案化一组开口以在邻近测量测量区域的区域中的FinFET器件中形成一组鳍片，在FinFET器件上沉积氧化物层，以及平坦化FinFET器件，以形成平面度量板 计量测量领域。

公开(公告)号：US20150287795A1

公开(公告)日：2015-10-08

申请号：US14244261

申请日：2014-04-03

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Sandeep Gaan ,  Sipeng Gu

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L21/311

CPC classification number: H01L29/66795 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/41791 ,  H01L29/785

Abstract: Processes for preparing an integrated circuit for contact landing, processes for fabricating an integrated circuit, and integrated circuits prepared according to these processes are provided herein. An exemplary process for preparing an integrated circuit for contact landing includes providing a semiconductor structure that includes a transistor with source and drain regions, wherein at least one of the source and drain regions has a shaped contact structure overlaid with a contact etch stop layer and a pre-metal dielectric material. The pre-metal dielectric material is removed with one or more anisotropic etches, including at least one anisotropic etch selective to the pre-metal dielectric material. And, the contact etch stop layer overlaying the shaped contact structure is removed with a third anisotropic etch selective to the contact etch stop layer material to expose the shaped contact structure.

Abstract translation: 本文提供了用于制备用于接触着陆的集成电路，用于制造集成电路的工艺，以及根据这些工艺制备的集成电路的工艺。 用于制备用于接触着陆的集成电路的示例性方法包括提供包括具有源区和漏区的晶体管的半导体结构，其中源极和漏极区中的至少一个具有覆盖有接触蚀刻停止层的成形接触结构和 预金属介电材料。 用一种或多种各向异性蚀刻去除预金属介电材料，包括对前金属介电材料选择性的至少一种各向异性蚀刻。 并且，用接触蚀刻停止层材料选择性的第三各向异性蚀刻去除覆盖成形接触结构的接触蚀刻停止层，以露出成形的接触结构。

公开(公告)号：US20210043766A1

公开(公告)日：2021-02-11

申请号：US16533835

申请日：2019-08-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Baofu Zhu ,  Shesh Mani Pandey ,  Jiehui Shu ,  Sipeng Gu ,  Haiting Wang

IPC: H01L29/78 ,  H01L29/66

Abstract: A laterally diffused metal-oxide semiconductor (LDMOS) device is disclosed. The LDMOS FET includes a gate structure between a source region and a drain region over a p-type semiconductor substrate; and a trench isolation partially under the gate structure and between the gate structure and the drain region. A p-well is under and adjacent the source region; and an n-well is under and adjacent the drain region. A counter doping region abuts and is between the p-well and the n-well, and is directly underneath the gate structure. The counter doping region increases drain-source breakdown voltage compares to conventional approaches.

公开(公告)号：US10832839B1

公开(公告)日：2020-11-10

申请号：US16570575

申请日：2019-09-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Scott Beasor ,  Haiting Wang ,  Sipeng Gu ,  Jiehui Shu

IPC: H01C7/22 ,  H01C1/012 ,  H01C17/00 ,  H01L23/522 ,  H01L49/02

Abstract: Device structures and fabrication methods for an on-chip resistor. A dielectric layer includes a trench with a bottom and a sidewall arranged to surround the bottom. A metal layer is disposed on the dielectric layer at the sidewall of the trench. The metal layer includes a surface that terminates the metal layer at the bottom of the trench to define a discontinuity that extends along a length of the trench.

公开(公告)号：US10818557B2

公开(公告)日：2020-10-27

申请号：US16026130

申请日：2018-07-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sipeng Gu ,  Akshey Sehgal ,  Xinyuan Dou ,  Sunil K. Singh ,  Ravi P. Srivastava ,  Haiting Wang ,  Scott H. Beasor

IPC: H01L21/8234 ,  H01L29/423 ,  H01L23/48 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/49 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/66 ,  H01L29/08

Abstract: This disclosure is directed to an integrated circuit (IC) structure. The IC structure may include a semiconductor structure including two source/drain regions; a metal gate positioned on the semiconductor structure adjacent to and between the source/drain regions; a metal cap with a different metal composition than the metal gate and having a thickness in the range of approximately 0.5 nanometer (nm) to approximately 5 nm positioned on the metal gate; a first dielectric cap layer positioned above the semiconductor structure; an inter-layer dielectric (ILD) positioned above the semiconductor structure and laterally abutting both the metal cap and the metal gate, wherein an upper surface of the ILD has a greater height above the semiconductor structure than an upper surface of the metal gate; a second dielectric cap layer positioned on the ILD and above the metal cap; and a contact on and in electrical contact with the metal cap.

公开(公告)号：US10580857B2

公开(公告)日：2020-03-03

申请号：US16010694

申请日：2018-06-18

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Yanzhen Wang ,  Xinyuan Dou ,  Hongliang Shen ,  Sipeng Gu

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762

Abstract: A shallow trench isolation (STI) structure is formed from a conventional STI trench structure of a first dielectric material extending into the substrate. The conventional STI structure undergoes further processing: removing a first portion of the dielectric material and adjacent portions of the semiconductor substrate to create a first recess, and then removing another portion of the dielectric material to create a second recess in just the dielectric material. A nitride spacer layer is formed above the remaining dielectric material and on the sidewalls of the substrate. A second dielectric material is formed on the spacer layer and fills the remainder of first and second recesses to a lever above the substrate. A nitride capping layer and another dielectric layer are disposed above the second material, thereby substantially encasing the STI structure in nitride. This provides a taller STI structure that results in a better fin profile during a subsequent fin reveal process.

公开(公告)号：US20190386100A1

公开(公告)日：2019-12-19

申请号：US16010694

申请日：2018-06-18

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Yanzhen Wang ,  Xinyuan Dou ,  Hongliang Shen ,  Sipeng Gu

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/762 ,  H01L21/02 ,  H01L29/66

Abstract: A shallow trench isolation (STI) structure is formed from a conventional STI trench structure of a first dielectric material extending into the substrate. The conventional STI structure undergoes further processing: removing a first portion of the dielectric material and adjacent portions of the semiconductor substrate to create a first recess, and then removing another portion of the dielectric material to create a second recess in just the dielectric material. A nitride spacer layer is formed above the remaining dielectric material and on the sidewalls of the substrate. A second dielectric material is formed on the spacer layer and fills the remainder of first and second recesses to a lever above the substrate. A nitride capping layer and another dielectric layer are disposed above the second material, thereby substantially encasing the STI structure in nitride. This provides a taller STI structure that results in a better fin profile during a subsequent fin reveal process.

公开(公告)号：US10347531B2

公开(公告)日：2019-07-09

申请号：US15438828

申请日：2017-02-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sipeng Gu ,  Xusheng Wu ,  Xinyuan Dou ,  Xiaobo Chen ,  Guoliang Zhu ,  Wenhe Lin ,  Jeffrey Chee

IPC: H01L21/768 ,  H01L23/535 ,  H01L23/532

Abstract: Disclosed are a method of forming an integrated circuit (IC) structure with robust metal plugs and the resulting IC structure. In the method, openings are formed in an interlayer dielectric layer to expose semiconductor device surfaces. The openings are lined with a two-layer liner, which includes conformal metal and barrier layers, and subsequently filled with a metal layer. However, instead of waiting until after the liner is formed to perform a silicidation anneal, as is conventionally done, the silicidation anneal is performed between deposition of the two liner layers. This is particularly useful because, as determined by the inventors, performing the silicidation anneal prior to depositing the conformal barrier layer prevents the formation of microcracks in the conformal barrier layer. Prevention of such microcracks, in turn, prevents any metal from the metal layer from protruding into the area between the two liner layers and/or completely through the liner.

公开(公告)号：US10347528B1

公开(公告)日：2019-07-09

申请号：US15912975

申请日：2018-03-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sunil K. Singh ,  Ravi P. Srivastava ,  Sipeng Gu ,  Akshey Sehgal

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Methods of forming an interconnect of an IC are disclosed. The methods etch a wire trench opening partially into an ILD layer using a hard mask, and form a metal liner sidewall spacer on sidewalls of the wire trench opening, prior to etching via openings that create a via-wire opening with the wire trench opening. The metal liner sidewall spacer protects against chamfering during the via etch and/or removal of an etch stop layer over conductive structures in an underlying ILD layer. In one embodiment, a barrier liner is deposited over the metal liner sidewall spacer, creating a double layered sidewall spacer on the sidewalls of the wire trench opening portion of the via-wire opening. A conductor is deposited to form a unitary via-wire conductive structure. An interconnect includes the double layered sidewall spacer on the sidewalls of a wire trench opening portion of the via-wire conductive structure.