公开(公告)号：US08518774B2

公开(公告)日：2013-08-27

申请号：US12053398

申请日：2008-03-21

申请人： Pierre Fazan

发明人： Pierre Fazan

IPC分类号： H01L29/06

CPC分类号： H01L27/10805 ,  H01L21/84 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/10847 ,  H01L27/1203 ,  H01L29/7841

摘要： Embodiments of a manufacturing process flow for producing standalone memory devices that can achieve bit cell sizes on the order of 4F2 or 5F2, and that can be applied to common source/drain, separate source/drain, or common source only or common drain only transistor arrays. Active area and word line patterns are formed as perpendicularly-arranged straight lines on a Silicon-on-Insulator substrate. The intersections of the active area and spaces between word lines define contact areas for the connection of vias and metal line layers. Insulative spacers are used to provide an etch mask pattern that allows the selective etching of contact areas as a series of linear trenches, thus facilitating straight line lithography techniques. Embodiments of the manufacturing process remove first layer metal (metal-1) islands and form elongated vias, in a succession of processing steps to build dense memory arrays.

摘要翻译： 用于制造独立存储器件的制造工艺流程的实施例，其可以实现4F2或5F2的数量级的位单元尺寸，并且可以应用于公共源极/漏极，单独的源极/漏极或仅公共源极或仅公共漏极晶体管 阵列 有源区域和字线图案在绝缘体上硅衬底上形成为垂直布置的直线。 活动区域和字线间的交点定义用于连接通孔和金属线层的接触区域。 使用绝缘间隔物来提供蚀刻掩模图案，其允许将接触区域选择性地蚀刻为一系列线性沟槽，从而便于直线光刻技术。 制造过程的实施例在连续的处理步骤中去除第一层金属（金属-1）岛并形成细长的通孔以构建密集的存储器阵列。

公开(公告)号：US20080165577A1

公开(公告)日：2008-07-10

申请号：US11904978

申请日：2007-09-28

申请人： Pierre Fazan ,  Serguel Okhonin

发明人： Pierre Fazan ,  Serguel Okhonin

IPC分类号： G11C11/34 ,  G11C7/00

CPC分类号： H01L27/108 ,  G11C11/403 ,  G11C11/404 ,  G11C11/5621 ,  G11C2211/4016 ,  H01L21/84 ,  H01L27/10802 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841 ,  H04N5/3355 ,  Y10S257/905 ,  Y10S257/907 ,  Y10S438/982

摘要： A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate and the drain and between the source and the drain.

摘要翻译： 公开了诸如存储器件或辐射检测器的半导体器件，其中在衬底上形成数据存储单元。 每个数据存储单元包括具有源极，漏极和栅极的场效应晶体管，以及布置在源极和漏极之间的用于存储在体内产生的电荷的主体。 体内净电荷的大小可以通过施加到晶体管的输入信号来调节，并且可以通过在栅极和漏极之间施加电压信号来至少部分地抵消由输入信号调节净电荷 在源和漏之间。

公开(公告)号：US20070109896A1

公开(公告)日：2007-05-17

申请号：US11649945

申请日：2007-01-05

申请人： Pierre Fazan ,  Serguei Okhonin

发明人： Pierre Fazan ,  Serguei Okhonin

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/404 ,  G11C2211/4016 ,  G11C2211/4065 ,  G11C2211/4068 ,  H01L2924/15311

摘要： A data storage device such as a DRAM memory having a plurality of data storage cells 10 is disclosed. Each data storage cell 10 has a physical parameter which varies with time and represents one of two binary logic states. A selection circuit 16, writing circuits 18 and a refreshing circuit 22 apply input signals to the data storage cells to reverse the variation of the physical parameter with time of at least those cells representing one of the binary logic states by causing a different variation in the physical parameter of cells in one of said states than in the other.

公开(公告)号：US06969662B2

公开(公告)日：2005-11-29

申请号：US10450238

申请日：2002-06-05

申请人： Pierre Fazan ,  Serguei Okhonin

发明人： Pierre Fazan ,  Serguei Okhonin

IPC分类号： G01T1/24 ,  G11C11/403 ,  G11C11/404 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/786 ,  H01L31/10 ,  H01L21/336

CPC分类号： H01L27/108 ,  G11C11/403 ,  G11C11/404 ,  G11C11/5621 ,  G11C2211/4016 ,  H01L21/84 ,  H01L27/10802 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841 ,  H04N5/3355 ,  Y10S257/905 ,  Y10S257/907 ,  Y10S438/982

摘要： A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate 13. Each of the data storage cells includes a field effect transistor having a source 18, drain 22 and gate 28, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body 22 can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate 28 and the drain 22 and between the source 18 and the drain 22.

摘要翻译： 公开了诸如存储器件或辐射检测器的半导体器件，其中数据存储单元形成在衬底13上。 每个数据存储单元包括具有源极18，漏极22和栅极28的场效应晶体管，以及布置在源极和漏极之间的用于存储在体内产生的电荷的主体。 主体22中的净电荷的大小可以通过施加到晶体管的输入信号进行调整，并且可以通过在栅极28和栅极28之间施加电压信号来至少部分地抵消由输入信号调节净电荷 漏极22和源极18与漏极22之间。

公开(公告)号：US20050063224A1

公开(公告)日：2005-03-24

申请号：US10941692

申请日：2004-09-15

申请人： Pierre Fazan ,  Serguei Okhonin

发明人： Pierre Fazan ,  Serguei Okhonin

IPC分类号： G11C11/404 ,  H01L27/108 ,  G11C11/34

CPC分类号： G11C11/404 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/7841

摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a memory cell, architecture, and/or array and/or technique of writing or programming data into the memory cell (for example, a technique to write or program a logic low or State “0” in a memory cell employing an electrically floating body transistor. In this regard, the present invention programs a logic low or State “0” in the memory cell while the electrically floating body transistor is in the “OFF” state or substantially “OFF” state (for example, when the device has no (or practically no) channel and/or channel current between the source and drain). In this way, the memory cell may be programmed whereby there is little to no current/power consumption by the electrically floating body transistor and/or from memory array having a plurality of electrically floating body transistors.

摘要翻译： 这里描述和说明了许多发明。 在一个方面，本发明涉及将数据写入或编程到存储器单元中的存储器单元，架构和/或阵列和/或技术（例如，写入或编程逻辑低或状态“0”的技术 在这方面，本发明在电浮动体晶体管处于“关”状态或基本上“关”的情况下，在存储单元中编程逻辑低或状态“0” 状态（例如，当器件在源极和漏极之间没有（或几乎不存在）通道和/或沟道电流）时，可以对存储器单元进行编程，由此存储单元很少或没有电流/功耗 电浮体晶体管和/或具有多个电浮体晶体管的存储器阵列。

公开(公告)号：US06674169B2

公开(公告)日：2004-01-06

申请号：US09962003

申请日：2001-09-24

申请人： Gurtej S. Sandhu ,  Pierre Fazan

发明人： Gurtej S. Sandhu ,  Pierre Fazan

IPC分类号： H01L2348

CPC分类号： H01L21/31604 ,  C23C16/40 ,  H01L27/10852

摘要： A semiconductor device comprised of a substantially conformal layer of titanium silicon oxide deposited on a semiconductor substrate. The layer of titanium silicon oxide is substantially free of chlorine related impurities. The layer of titanium silicon oxide may have a ratio of silicon to titanium from about 0.1 to about 1.9. The layer of titanium silicon oxide may have a dielectric constant from about 10 to about 30, and a thickness from about 15 angstroms to about 500 angstroms.

摘要翻译： 一种半导体器件，包括沉积在半导体衬底上的基本上保形的氧化钛硅层。 钛氧化硅层基本上不含氯相关杂质。 钛硅氧化物层可以具有约0.1至约1.9的硅与钛的比例。 钛氧化硅层可以具有约10至约30的介电常数和约15埃至约500埃的厚度。

公开(公告)号：US6090670A

公开(公告)日：2000-07-18

申请号：US929138

申请日：1997-09-05

申请人： Gurtej Singh Sandhu ,  Pierre Fazan

发明人： Gurtej Singh Sandhu ,  Pierre Fazan

IPC分类号： H01L29/423 ,  H01L29/788 ,  H01L21/336 ,  H01L29/76 ,  H01L29/80

CPC分类号： H01L29/7885 ,  H01L29/42324

摘要： In a semiconductor fabrication method for forming a transistor structure upon a semiconductor substrate, a nitride layer is also formed over the semiconductor substrate. A gate oxide layer is formed over a region of the semiconductor substrate. The gate oxide layer has a relatively thinner oxide region over the nitride layer and a relatively thicker oxide region over the substrate adjacent the nitride layer. A transistor gate is formed extending over the relatively thinner oxide region and over the relatively thicker oxide region. The transistor thus formed is therefore asymmetric. A first transistor active region is formed in the vicinity of the relatively thicker oxide region and a second transistor active region is formed in the vicinity of the relatively thinner oxide region. The nitride layer can be formed by rapid thermal nitridization of the semiconductor substrate. The relatively thinner oxide region can be one-half as thick as the relatively thinner oxide region. The surface of the semiconductor substrate can be curved in the vicinity of the drain of the asymmetric transistor in order to permit the momentum of the charge carriers to facilitate penetration of the charge carriers into the gate.

摘要翻译： 在用于在半导体衬底上形成晶体管结构的半导体制造方法中，在半导体衬底上也形成氮化物层。 在半导体衬底的区域上形成栅氧化层。 栅极氧化物层在氮化物层上方具有相对较薄的氧化物区域，并且在邻近氮化物层的衬底上方相对较厚的氧化物区域。 晶体管栅极形成在相对较薄的氧化物区域上方并在相对较厚的氧化物区域上延伸。 因此，如此形成的晶体管是不对称的。 在相对较厚的氧化物区域附近形成第一晶体管有源区，并且在相对较薄的氧化物区域附近形成第二晶体管有源区。 可以通过半导体衬底的快速热氮化形成氮化物层。 相对较薄的氧化物区域可以是相对较薄的氧化物区域的一半厚度。 半导体衬底的表面可以在不对称晶体管的漏极附近弯曲，以允许电荷载流子的动量促进电荷载流子进入栅极。

公开(公告)号：US5939333A

公开(公告)日：1999-08-17

申请号：US655728

申请日：1996-05-30

申请人： Kelly T. Hurley ,  Li Li ,  Pierre Fazan ,  Zhiqiang Wu

发明人： Kelly T. Hurley ,  Li Li ,  Pierre Fazan ,  Zhiqiang Wu

IPC分类号： C23C16/02 ,  C23C16/34 ,  H01L21/314 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/3144 ,  C23C16/0272 ,  C23C16/345 ,  H01L21/76224

摘要： A silicon nitride deposition method includes providing a substrate surface including one or more component surfaces. At least a monolayer of silicon is predeposited on the one or more component surfaces of the substrate surface resulting in a substantially native oxide free uniform predeposited silicon substrate surface. Thereafter, a silicon nitride layer is deposited on the predeposited silicon substrate surface after the silicon predeposition. Further, another silicon nitride deposition method includes providing a silicon based substrate surface. The substrate surface is nitridated in an atmosphere of dimethylhydrazine, and thereafter, a silicon nitride layer is deposited on the nitridated surface. The nitridation of the substrate surface results in a thickness less than three monolayers of silicon nitride.

摘要翻译： 氮化硅沉积方法包括提供包括一个或多个部件表面的基板表面。 至少单层硅预沉积在衬底表面的一个或多个组件表面上，导致基本上无氧化的均匀的预沉积硅衬底表面。 此后，在硅预沉积之后，在预沉积的硅衬底表面上沉积氮化硅层。 此外，另一种氮化硅沉积方法包括提供硅基衬底表面。 将基板表面在二甲基肼的气氛中氮化，然后在氮化表面上沉积氮化硅层。 衬底表面的氮化导致厚度小于三层氮化硅单层。

公开(公告)号：US5866453A

公开(公告)日：1999-02-02

申请号：US527924

申请日：1995-09-14

申请人： Kirk D. Prall ,  Pierre Fazan ,  Trung Doan ,  Tyler Lowrey

发明人： Kirk D. Prall ,  Pierre Fazan ,  Trung Doan ,  Tyler Lowrey

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L21/20

CPC分类号： H01L27/10852 ,  H01L27/10808

摘要： An etch process for increasing the alignment tolerances between capacitor components and an adjacent contact corridor in Dynamic Random Access Memories. The etch process is implemented in a capacitor structure formed over a semiconductor substrate. The capacitor structure includes a first conductor, a dielectric layer on the first conductor and a second conductor on the dielectric layer. The second conductor has a horizontal region laterally adjacent to and extending away from the first conductor. The etch process comprises the steps of: (a) forming a layer of patterned photoresist over the second conductor, the photoresist being patterned to expose a portion of the horizontal region of the second conductor at a desired location of a contact corridor above a source/drain region in the substrate; (b) using the photoresist as an etch mask, anisotropically etching away the exposed portions of the horizontal region of the second conductor; and (c) using the photoresist again as an etch mask, isotropically etching away substantially all of the remaining portions of the horizontal region of the second conductor and thereby enlarging the area available for locating the contact corridor. Alternatively, the horizontal region of the second conductor is removed using a single isotropic etch.

摘要翻译： 用于增加动态随机存取存储器中电容器组件与相邻触点走廊之间的对准公差的蚀刻工艺。 蚀刻工艺在半导体衬底上形成的电容器结构中实现。 电容器结构包括第一导体，第一导体上的电介质层和电介质层上的第二导体。 第二导体具有横向邻近并远离第一导体延伸的水平区域。 蚀刻工艺包括以下步骤：（a）在第二导体上形成图案化光致抗蚀剂层，光刻胶被图案化以在第二导体的水平区域的一个源/ 漏极区域; （b）使用光致抗蚀剂作为蚀刻掩模，各向异性地蚀刻掉第二导体的水平区域的暴露部分; 和（c）再次使用光致抗蚀剂作为蚀刻掩模，各向同性地蚀刻掉第二导体的水平区域的基本上所有其余部分，从而扩大可用于定位接触走廊的面积。 或者，使用单个各向同性蚀刻去除第二导体的水平区域。

公开(公告)号：US5393683A

公开(公告)日：1995-02-28

申请号：US887785

申请日：1992-05-26

申请人： Viju K. Mathews ,  Charles H. Dennison ,  Pierre Fazan ,  Roy Maddox ,  Akram Ditali

发明人： Viju K. Mathews ,  Charles H. Dennison ,  Pierre Fazan ,  Roy Maddox ,  Akram Ditali

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L21/265

CPC分类号： H01L21/28202 ,  H01L21/28211 ,  H01L29/513 ,  H01L29/518

摘要： The present invention includes a method of forming semiconductor oxide layers and, in particular, gate oxide layers, in MOS semiconductor devices formed on silicon substrates. The method includes the steps of forming a first silicon oxide sublayer on the silicon substrate in an atmosphere including primarily oxygen, and forming a second silicon oxide sublayer over the first sublayer in an atmosphere including primarily nitrous oxide (N.sub.2 O). Preferably, the first and second sublayers represent 80 percent and 20 percent, respectively, of the silicon oxide layer.

摘要翻译： 本发明包括在形成在硅衬底上的MOS半导体器件中形成半导体氧化物层，特别是栅极氧化物层的方法。 该方法包括以下步骤：在主要包含氧的气​​氛中在硅衬底上形成第一氧化硅子层，并在主要包括一氧化二氮（N2O）的气氛中在第一子层上形成第二氧化硅层。 优选地，第一和第二子层分别代表氧化硅层的80％和20％。