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    Etch process for aligning a capacitor structure and an adjacent contact corridor
    1.
    发明授权
    Etch process for aligning a capacitor structure and an adjacent contact corridor 有权
    用于对齐电容器结构和相邻触点走廊的蚀刻工艺

    公开(公告)号：US06274423B1

    公开(公告)日：2001-08-14

    申请号：US09236761

    申请日：1999-01-25

    申请人： Kirk D. Prall ,  Pierre Fazan ,  Trung Doan ,  Tyler Lowrey

    发明人： Kirk D. Prall ,  Pierre Fazan ,  Trung Doan ,  Tyler Lowrey

    IPC分类号： H01L218242

    CPC分类号： H01L27/10852 ,  H01L27/10808

    摘要： An etch process for increasing the alignment tolerances between capacitor components and an adjacent contact corridor in Dynamic Random Access Memories. The etch process is implemented in a capacitor structure formed over a semiconductor substrate The capacitor structure includes a first conductor, a dielectric layer on the first conductor and a second conductor on the dielectric layer. The second conductor has a horizontal region laterally adjacent to and extending away from the first conductor. The etch process comprises the steps of: (a) forming a layer of patterned photoresist over the second conductor, the photoresist being patterned to expose a portion of the horizontal region of the second conductor at a desired location of a contact corridor above a source/drain region in the substrate; (b) using the photoresist as an etch mask, anisotropically etching away the exposed portions of the horizontal region of the second conductor; and (c) using the photoresist again as an etch mask, isotropically etching away substantially all of the remaining portions of the horizontal region of the second conductor and thereby enlarging the area available for locating the contact corridor. Alternatively, the horizontal region of the second conductor is removed using a single isotropic etch.

    摘要翻译： 用于增加动态随机存取存储器中电容器组件与相邻触点走廊之间的对准公差的蚀刻工艺。 该蚀刻工艺在形成于半导体衬底上的电容器结构中实施。电容器结构包括第一导体，第一导体上的电介质层和介电层上的第二导体。 第二导体具有横向邻近并远离第一导体延伸的水平区域。 蚀刻工艺包括以下步骤：（a）在第二导体上形成图案化光致抗蚀剂层，光刻胶被图案化以在第二导体的水平区域的一个源/ 漏极区域; （b）使用光致抗蚀剂作为蚀刻掩模，各向异性地蚀刻掉第二导体的水平区域的暴露部分; 和（c）再次使用光致抗蚀剂作为蚀刻掩模，各向同性地蚀刻掉第二导体的水平区域的基本上所有其余部分，从而扩大可用于定位接触走廊的面积。 或者，使用单个各向同性蚀刻去除第二导体的水平区域。

    Etch process for aligning a capacitor structure and an adjacent contact corridor
    2.
    发明授权
    Etch process for aligning a capacitor structure and an adjacent contact corridor 失效
    用于对齐电容器结构和相邻触点走廊的蚀刻工艺

    公开(公告)号：US5866453A

    公开(公告)日：1999-02-02

    申请号：US527924

    申请日：1995-09-14

    申请人： Kirk D. Prall ,  Pierre Fazan ,  Trung Doan ,  Tyler Lowrey

    发明人： Kirk D. Prall ,  Pierre Fazan ,  Trung Doan ,  Tyler Lowrey

    IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L21/20

    CPC分类号： H01L27/10852 ,  H01L27/10808

    摘要： An etch process for increasing the alignment tolerances between capacitor components and an adjacent contact corridor in Dynamic Random Access Memories. The etch process is implemented in a capacitor structure formed over a semiconductor substrate. The capacitor structure includes a first conductor, a dielectric layer on the first conductor and a second conductor on the dielectric layer. The second conductor has a horizontal region laterally adjacent to and extending away from the first conductor. The etch process comprises the steps of: (a) forming a layer of patterned photoresist over the second conductor, the photoresist being patterned to expose a portion of the horizontal region of the second conductor at a desired location of a contact corridor above a source/drain region in the substrate; (b) using the photoresist as an etch mask, anisotropically etching away the exposed portions of the horizontal region of the second conductor; and (c) using the photoresist again as an etch mask, isotropically etching away substantially all of the remaining portions of the horizontal region of the second conductor and thereby enlarging the area available for locating the contact corridor. Alternatively, the horizontal region of the second conductor is removed using a single isotropic etch.

    摘要翻译： 用于增加动态随机存取存储器中电容器组件与相邻触点走廊之间的对准公差的蚀刻工艺。 蚀刻工艺在半导体衬底上形成的电容器结构中实现。 电容器结构包括第一导体，第一导体上的电介质层和电介质层上的第二导体。 第二导体具有横向邻近并远离第一导体延伸的水平区域。 蚀刻工艺包括以下步骤：（a）在第二导体上形成图案化光致抗蚀剂层，光刻胶被图案化以在第二导体的水平区域的一个源/ 漏极区域; （b）使用光致抗蚀剂作为蚀刻掩模，各向异性地蚀刻掉第二导体的水平区域的暴露部分; 和（c）再次使用光致抗蚀剂作为蚀刻掩模，各向同性地蚀刻掉第二导体的水平区域的基本上所有其余部分，从而扩大可用于定位接触走廊的面积。 或者，使用单个各向同性蚀刻去除第二导体的水平区域。

    SEMICONDUCTOR STRUCTURES INCLUDING VERTICAL DIODE STRUCTURES AND METHODS OF MAKING THE SAME
    3.
    发明申请
    SEMICONDUCTOR STRUCTURES INCLUDING VERTICAL DIODE STRUCTURES AND METHODS OF MAKING THE SAME 失效
    包括垂直二极管结构的半导体结构及其制造方法

    公开(公告)号：US20080032480A1

    公开(公告)日：2008-02-07

    申请号：US11869012

    申请日：2007-10-09

    申请人： Fernando Gonzalez ,  Tyler Lowrey ,  Trung Doan ,  Raymond Turi ,  Graham Wolstenholme

    发明人： Fernando Gonzalez ,  Tyler Lowrey ,  Trung Doan ,  Raymond Turi ,  Graham Wolstenholme

    IPC分类号： H01L21/20 ,  H01L29/00

    CPC分类号： H01L21/02667 ,  H01L21/02532 ,  H01L21/2022 ,  H01L27/0814 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/24 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/861 ,  H01L45/04 ,  H01L45/145 ,  Y10S257/903 ,  Y10S257/91 ,  Y10S438/979

    摘要： Semiconductor structures and methods of making a vertical diode structure are provided. The vertical diode structure may have associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer may be formed over the interior surface of the diode opening and contacting the active region. The diode opening may initially be filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that may be heavily doped with a first type dopant and a bottom portion that may be lightly doped with a second type dopant. The top portion may be bounded by the bottom portion so as not to contact the titanium silicide layer. In one embodiment of the vertical diode structure, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.

    摘要翻译： 提供了制造垂直二极管结构的半导体结构和方法。 垂直二极管结构可以具有延伸穿过绝缘层并接触硅晶片上的有源区的二极管开口。 硅化钛层可以形成在二极管开口的内表面上并与活性区接触。 二极管开口最初可以填充非晶硅插塞，其在沉积期间被掺杂并随后重结晶以形成大晶粒多晶硅。 硅插头具有可以重掺杂第一类型掺杂剂的顶部部分和可以轻掺杂第二类型掺杂剂的底部部分。 顶部可以由底部限定，以便不与硅化钛层接触。 在垂直二极管结构的一个实施例中，可编程电阻器接触硅插头的顶部并且金属线接触可编程电阻器。

    Vertical diode structures
    4.
    发明申请
    Vertical diode structures 有权
    垂直二极管结构

    公开(公告)号：US20050280117A1

    公开(公告)日：2005-12-22

    申请号：US11210401

    申请日：2005-08-24

    申请人： Fernando Gonzalez ,  Tyler Lowrey ,  Trung Doan ,  Raymond Turi ,  Graham Wolstenholme

    发明人： Fernando Gonzalez ,  Tyler Lowrey ,  Trung Doan ,  Raymond Turi ,  Graham Wolstenholme

    IPC分类号： H01L21/329 ,  H01L27/08 ,  H01L29/00 ,  H01L29/861

    CPC分类号： H01L21/02667 ,  H01L21/02532 ,  H01L21/2022 ,  H01L27/0814 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/24 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/861 ,  H01L45/04 ,  H01L45/145 ,  Y10S257/903 ,  Y10S257/91 ,  Y10S438/979

    摘要： A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.

    摘要翻译： 提供了一种制造垂直二极管的方法，所述垂直二氧化物具有与其相连的二极管开口，其延伸穿过绝缘层并接触硅晶片上的有源区。 硅化钛层覆盖二极管开口的内表面并接触有源区。 二极管开口最初填充有非晶硅插塞，其在沉积期间被掺杂，随后再结晶以形成大晶粒多晶硅。 硅插头具有重掺杂有第一类型掺杂剂的顶部部分和轻掺杂有第二类型掺杂剂的底部部分。 顶部由底部界定，以便不与硅化钛层接触。 对于垂直二极管的一个实施例，可编程电阻器接触硅插头的顶部并且金属线接触可编程电阻器。

    Semiconductor device having recess and planarized layers and method of fabrication
    5.
    发明申请
    Semiconductor device having recess and planarized layers and method of fabrication 失效
    具有凹陷和平坦化层的半导体器件及其制造方法

    公开(公告)号：US20050212070A1

    公开(公告)日：2005-09-29

    申请号：US11141664

    申请日：2005-06-01

    申请人： Trung Doan ,  Tyler Lowrey

    发明人： Trung Doan ,  Tyler Lowrey

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L31/0232

    CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42336 ,  H01L29/7881

    摘要： A method for forming a floating gate semiconductor device such as an electrically erasable programmable read only memory is provided. The device includes a silicon substrate having an electrically isolated active area. A gate oxide, as well as other components of a FET (e.g., source, drain) are formed in the active area. A self aligned floating gate is formed by depositing a conductive layer (e.g., polysilicon) into the recess and over the gate oxide. The conductive layer is then chemically mechanically planarized to an endpoint of the isolation layer so that all of the conductive layer except material in the recess and on the gate oxide is removed. Following formation of the floating gate an insulating layer is formed on the floating gate and a control gate is formed on the insulating layer.

    摘要翻译： 提供了一种用于形成诸如电可擦除可编程只读存储器的浮置栅极半导体器件的方法。 该器件包括具有电隔离的有源区的硅衬底。 栅极氧化物以及FET的其它部件（例如，源极，漏极）形成在有源区域中。 通过将导电层（例如多晶硅）沉积到栅极氧化物上而形成自对准浮栅。 然后将导电层化学机械平面化到隔离层的端点，使得去除凹部中和栅极氧化物上的材料以外的所有导电层。 在形成浮栅之后，在浮栅上形成绝缘层，在绝缘层上形成控制栅。

    Memory array having floating gate semiconductor device
    6.
    发明申请
    Memory array having floating gate semiconductor device 失效
    具有浮置栅极半导体器件的存储器阵列

    公开(公告)号：US20080054342A1

    公开(公告)日：2008-03-06

    申请号：US11933728

    申请日：2007-11-01

    申请人： Trung Doan ,  Tyler Lowrey

    发明人： Trung Doan ,  Tyler Lowrey

    IPC分类号： H01L29/788

    CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42336 ,  H01L29/7881

    摘要： A method for forming a floating gate semiconductor device such as an electrically erasable programmable read only memory is provided. The device includes a silicon substrate having an electrically isolated active area. A gate oxide, as well as other components of a FET (e.g., source, drain) are formed in the active area. A self aligned floating gate is formed by depositing a conductive layer (e.g., polysilicon) into the recess and over the gate oxide. The conductive layer is then chemically mechanically planarized to an endpoint of the isolation layer so that all of the conductive layer except material in the recess and on the gate oxide is removed. Following formation of the floating gate an insulating layer is formed on the floating gate and a control gate is formed on the insulating layer.

    摘要翻译： 提供了一种用于形成诸如电可擦除可编程只读存储器的浮置栅极半导体器件的方法。 该器件包括具有电隔离的有源区的硅衬底。 栅极氧化物以及FET的其它部件（例如，源极，漏极）形成在有源区域中。 通过将导电层（例如多晶硅）沉积到栅极氧化物上而形成自对准浮栅。 然后将导电层化学机械平面化到隔离层的端点，使得去除凹部中和栅极氧化物上的材料以外的所有导电层。 在形成浮栅之后，在浮栅上形成绝缘层，在绝缘层上形成控制栅。

    Semiconductor device having recess and planarized layers
    7.
    发明申请
    Semiconductor device having recess and planarized layers 失效
    具有凹槽和平坦化层的半导体器件

    公开(公告)号：US20060115987A1

    公开(公告)日：2006-06-01

    申请号：US11331573

    申请日：2006-01-13

    申请人： Trung Doan ,  Tyler Lowrey

    发明人： Trung Doan ,  Tyler Lowrey

    IPC分类号： H01L21/461

    CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42336 ,  H01L29/7881

    摘要： A method for forming a floating gate semiconductor device such as an electrically erasable programmable read only memory is provided. The device includes a silicon substrate having an electrically isolated active area. A gate oxide, as well as other components of a FET (e.g., source, drain) are formed in the active area. A self aligned floating gate is formed by depositing a conductive layer (e.g., polysilicon) into the recess and over the gate oxide. The conductive layer is then chemically mechanically planarized to an endpoint of the isolation layer so that all of the conductive layer except material in the recess and on the gate oxide is removed. Following formation of the floating gate an insulating layer is formed on the floating gate and a control gate is formed on the insulating layer.

    摘要翻译： 提供了一种用于形成诸如电可擦除可编程只读存储器的浮置栅极半导体器件的方法。 该器件包括具有电隔离的有源区的硅衬底。 栅极氧化物以及FET的其它部件（例如，源极，漏极）形成在有源区域中。 通过将导电层（例如多晶硅）沉积到栅极氧化物上而形成自对准浮栅。 然后将导电层化学机械平面化到隔离层的端点，使得去除凹部中和栅极氧化物上的材料以外的所有导电层。 在形成浮栅之后，在浮栅上形成绝缘层，在绝缘层上形成控制栅。

    Wafer with vertical diode structures
    8.
    发明申请
    Wafer with vertical diode structures 有权
    具有垂直二极管结构的晶圆

    公开(公告)号：US20060008975A1

    公开(公告)日：2006-01-12

    申请号：US11210357

    申请日：2005-08-24

    申请人： Fernando Gonzalez ,  Tyler Lowrey ,  Trung Doan ,  Raymond Turi ,  Graham Wolstenholme

    发明人： Fernando Gonzalez ,  Tyler Lowrey ,  Trung Doan ,  Raymond Turi ,  Graham Wolstenholme

    IPC分类号： H01L21/8234 ,  H01L29/00

    CPC分类号： H01L21/02667 ,  H01L21/02532 ,  H01L21/2022 ,  H01L27/0814 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/24 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/861 ,  H01L45/04 ,  H01L45/145 ,  Y10S257/903 ,  Y10S257/91 ,  Y10S438/979

    摘要： A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.

    摘要翻译： 提供了一种制造垂直二极管的方法，所述垂直二氧化物具有与其相连的二极管开口，其延伸穿过绝缘层并接触硅晶片上的有源区。 硅化钛层覆盖二极管开口的内表面并接触有源区。 二极管开口最初填充有非晶硅插塞，其在沉积期间被掺杂，随后再结晶以形成大晶粒多晶硅。 硅插头具有重掺杂有第一类型掺杂剂的顶部部分和轻掺杂有第二类型掺杂剂的底部部分。 顶部由底部界定，以便不与硅化钛层接触。 对于垂直二极管的一个实施例，可编程电阻器接触硅插头的顶部并且金属线接触可编程电阻器。