公开(公告)号：US10026477B2

公开(公告)日：2018-07-17

申请号：US15329845

申请日：2015-01-28

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Jianhua Yang ,  Ning Ge ,  John Paul Strachan ,  Gary Gibson ,  Warren Jackson

IPC: G11C11/00 ,  G11C13/00

Abstract: In one example, a volatile selector is switched from a low conduction state to a first high conduction state with a first voltage level and then the first voltage level is removed to activate a relaxation time for the volatile selector. The relaxation time is defined as the time the first volatile selector transitions from the high conduction state back to the low conduction state. The volatile selector is switched with a second voltage level of opposite polarity to the first voltage level to significantly reduce the relaxation time of the volatile selector.

公开(公告)号：US10008264B2

公开(公告)日：2018-06-26

申请号：US15521542

申请日：2014-10-23

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Ning Ge ,  Jianhua Yang ,  John Paul Strachan ,  Miao Hu

IPC: G11C13/00 ,  G06F17/16 ,  G06F17/11

CPC classification number: G11C13/0069 ,  G06F17/11 ,  G06F17/16 ,  G06G7/16 ,  G11C7/1006 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C2213/15 ,  G11C2213/77

Abstract: A method of obtaining a dot product includes applying a number of first voltages to a corresponding number of row lines within a memristive cross-bar array to change the resistive values of a corresponding number of memristors located a junctions between the row lines and a number of column lines. The first voltages define a corresponding number of values within a matrix, respectively. The method further includes applying a number of second voltages to a corresponding number of the row lines within the memristive cross-bar array. The second voltages define a corresponding number of vector values. The method further includes collecting the output currents from the column lines. The collected output currents define the dot product.

公开(公告)号：US09934852B2

公开(公告)日：2018-04-03

申请号：US15329207

申请日：2015-01-23

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Kyung Min Kim ,  Ning Ge ,  Jianhua Yang

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C7/062 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0061 ,  G11C2207/063

Abstract: A method of sensing an output signal in a crossbar array is described. In the method, a selecting voltage is applied to a target memory element of the crossbar array. Also in the method, a non-selecting voltage is applied to non-target memory elements of the crossbar array. Further in the method, a target output that is associated with the target memory element is isolated, with sensing circuitry, from a sneak output based on a time delay between arrival of the target output and the sneak output and the target output is sensed.

公开(公告)号：US09837147B2

公开(公告)日：2017-12-05

申请号：US15307486

申请日：2014-04-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Ning Ge ,  Jianhua Yang ,  Adam L. Ghozeil ,  Brent Buchanan

IPC: G11C13/00 ,  G11C27/02

CPC classification number: G11C13/0038 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C27/024 ,  G11C2013/0054 ,  G11C2013/0066 ,  G11C2013/0076 ,  G11C2013/0092

Abstract: A device for regulating memristor switching pulses is described. The device includes a voltage source to supply a voltage to a memristor. The device also includes a voltage detector to detect a memristor voltage. The memristor voltage is based on an initial resistance state of the memristor and the voltage supplied by the voltage source. The device also includes a comparator to compare the memristor voltage with a target voltage value for the memristor. The device also includes a feedback loop to indicate to a control switch when the memristor voltage is at least equal to the target voltage value. The device also includes a control switch to cut off the memristor from the voltage source when the memristor voltage is at least equal to the target voltage value.

公开(公告)号：US20170316828A1

公开(公告)日：2017-11-02

申请号：US15522364

申请日：2014-10-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Miao Hu ,  Jianhua Yang ,  John Paul Strachan ,  Ning Ge

IPC: G11C13/00 ,  G06F17/16

CPC classification number: G11C13/0069 ,  G06F17/16 ,  G06G7/16 ,  G11C13/0026 ,  G11C13/004 ,  G11C2213/77

Abstract: A double bias dot-product engine for vector processing is described. The dot product engine includes a crossbar array having N×M memory elements to store information corresponding to values contained in an N×M matrix, each memory element being a memristive storage device. First and second vector input registers including N voltage inputs, each voltage input corresponding to a value contained in a vector having N×1 values. The vector input registers are connected to the crossbar array to supply voltage inputs to each of N row electrodes at two locations along the electrode. A vector output register is also included to receive voltage outputs from each of M column electrodes.

公开(公告)号：US20170199746A1

公开(公告)日：2017-07-13

申请号：US15323945

申请日：2014-10-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Vincent Nguyen ,  Chanh V. Hua ,  Ning Ge ,  Naveen Marulimanohar

IPC: G06F9/44 ,  G06F1/32

CPC classification number: G06F9/4406 ,  G06F1/3287 ,  G06F9/4401 ,  G06F11/3058 ,  G06F11/3089

Abstract: A system management controller with a consolidated memory is disclosed. The example computing device includes a processor to host an operating system and a system memory to be used by the processor to execute instructions. The computing device also includes a management controller to enable out-of-band management of the computing device. The management controller includes a consolidated memory device. A first memory block of the consolidated memory device is used by the management controller as a working memory and a second memory block of the consolidated memory device is used for long-term storage of programming instructions.

公开(公告)号：US20170077179A1

公开(公告)日：2017-03-16

申请号：US15308923

申请日：2014-05-05

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Jianhua Yang ,  Ning Ge ,  Zhiyong Li

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2418 ,  H01L27/2409 ,  H01L45/00 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16

Abstract: A selector with an oxide-based layer includes an oxide-based layer that has a first region and a second region. The first region contains a metal oxide in a first oxidation state, and the second region contains the metal oxide in a second oxidation state. The first region also forms a part of each of two opposite faces of the oxide-based layer.

Abstract translation: 具有氧化物层的选择器包括具有第一区域和第二区域的氧化物基层。 第一区域包含处于第一氧化态的金属氧化物，第二区域包含处于第二氧化态的金属氧化物。 第一区域还形成氧化物基层的两个相对面中的每一个的一部分。

公开(公告)号：US10970625B2

公开(公告)日：2021-04-06

申请号：US15500073

申请日：2014-11-03

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Miao Hu ,  Jianhua Yang ,  Ning Ge

IPC: G06N3/063 ,  G06N3/04 ,  G06N3/08

Abstract: A device according to examples of the present disclosure includes a crossbar array including a cell. The cell includes a first resistance switch and a second resistance switch connected in series with the first resistance switch. The first and second resistance switches have different switching characteristics. One of the first and second resistance switches may act as a switch, while the other of the first and second resistance switches may weight the switching behavior of the one that acts as the switch.

公开(公告)号：US10418810B2

公开(公告)日：2019-09-17

申请号：US15540192

申请日：2015-01-28

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Brent Buchanan ,  Richard J. Auletta ,  Ning Ge

IPC: H02H9/04 ,  G11C13/00 ,  H01L27/02 ,  H01L45/00 ,  H01L27/092 ,  H01L21/8234 ,  G11C29/50

Abstract: In the examples provided herein, an electrostatic discharge (ESD) recording circuit has a first memristive element coupled to a pin of an integrated circuit. The first memristive element switches from a first resistance to a second resistance when an ESD event occurs at the pin, and the first resistance is less than the second resistance. The ESD recording circuit also has shunting circuitry to shunt energy from an additional ESD event away from the first memristive element.

公开(公告)号：US20180108403A1

公开(公告)日：2018-04-19

申请号：US15556361

申请日：2015-04-10

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Ning Ge ,  Jianhua Yang ,  Miao Hu ,  John Paul Strachan

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C7/04 ,  G11C13/0007 ,  G11C13/0033 ,  G11C13/0038 ,  G11C13/0069

Abstract: A temperature compensation circuit may comprise a temperature sensor to sense a temperature signal of a memristor crossbar array, a signal converter to convert the temperature signal to an electrical control signal, and a voltage compensation circuit to determine a compensation voltage based on the electrical control signal and pre-calibrated temperature data of the memristor crossbar array.